ST7LIT15BF0 STMicroelectronics, ST7LIT15BF0 Datasheet - Page 44

• Manufacturer Part Number: ST7LIT15BF0
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LIT15BF0

• Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow

ST7LITE1xB
POWER SAVING MODES (Cont’d)
Figure 27. ACTIVE-HALT Timing Overview
Figure 28. ACTIVE-HALT Mode Flow-chart
Notes:
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripherals clocked with an external clock
source can still be active.
3. Only the RTC1 interrupt and some specific inter-
rupts can exit the MCU from ACTIVE-HALT mode.
Refer to Table 5, “Interrupt Mapping,” on page 37
for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
44/159
1
[Active Halt Enabled]
INSTRUCTION
(AWUCSR.AWUEN=0)
HALT INSTRUCTION
RUN
(Active Halt enabled)
N
HALT
INTERRUPT
ACTIVE
HALT
Y
256 OR 4096 CPU
CYCLE DELAY
INTERRUPT
3)
256 OR 4096 CPU CLOCK
RESET
OR SERVICE INTERRUPT
FETCH RESET VECTOR
OR
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
I BIT
I BIT
I BIT
N
CYCLE
RESET
Y
1)
VECTOR
FETCH
DELAY
RUN
2)
2)
OFF
OFF
OFF
ON
ON
ON
X
ON
ON
ON
X
0
4)
4)
9.6 AUTO WAKE UP FROM HALT MODE
Auto Wake Up From Halt (AWUFH) mode is simi-
lar to Halt mode with the addition of a specific in-
ternal RC oscillator for wake-up (Auto Wake Up
from Halt Oscillator). Compared to ACTIVE-HALT
mode, AWUFH has lower power consumption (the
main clock is not kept running, but there is no ac-
curate realtime clock available.
It is entered by executing the HALT instruction
when the AWUEN bit in the AWUCSR register has
been set.
Figure 29. AWUFH Mode Block Diagram
As soon as HALT mode is entered, and if the
AWUEN bit has been set in the AWUCSR register,
the AWU RC oscillator provides a clock signal
(f
er and a programmable prescaler controlled by the
AWUPR register. The output of this prescaler pro-
vides the delay time. When the delay has elapsed
the AWUF flag is set by hardware and an interrupt
wakes-up the MCU from Halt mode. At the same
time the main oscillator is immediately turned on
and a 256 or 4096 cycle delay is used to stabilize
it. After this start-up delay, the CPU resumes oper-
ation by servicing the AWUFH interrupt. The AWU
flag and its associated interrupt are cleared by
software reading the AWUCSR register.
To compensate for any frequency dispersion of
the AWU RC oscillator, it can be calibrated by
measuring the clock frequency f
calculating the right prescaler value. Measurement
mode is enabled by setting the AWUM bit in the
AWUCSR register in Run mode. This connects
f
load timer, allowing the f
using the main oscillator clock as a reference time-
base.
AWU_RC
AWU_RC
f
AWU_RC
AWU RC
oscillator
divider
/64
to the input capture of the 12-bit Auto-Re-
). Its frequency is divided by a fixed divid-
prescaler/1 .. 255
to Timer input capture
AWUFH
AWU_RC
AWU_RC
to be measured
(ei0 source)
AWUFH
interrupt
and then