CYP15G0101DXB Cypress Semiconductor Corporation., CYP15G0101DXB Datasheet - Page 10

• Manufacturer Part Number: CYP15G0101DXB
• Description: Single-channel Hotlink Ii Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02031 Rev. *J
Pin Descriptions
Pin Name
BISTLE
RXLE
BOE[1:0]
LFI
JTAG Interface
TMS
TCLK
TDO
TDI
Power
V
GND
CC
I/O Characteristics Signal Description
LVTTL Input,
asynchronous,
internal pull-up
LVTTL Input,
asynchronous,
internal pull-up
LVTTL Input,
asynchronous,
internal pull-up
LVTTL Output,
Asynchronous
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-down
Three-State
LVTTL Output
LVTTL Input,
internal pull-up
CYP(V)(W)15G0101DXB Single-channel HOTLink II (continued)
Transmit and Receive BIST Latch Enable. Active HIGH. When BISTLE = HIGH, the
signals on the BOE[1:0] inputs directly control the transmit and receive BIST enables. When
the BOE[x] input is LOW, the associated transmit or receive channel is configured to
generate or compare the BIST sequence. When the BOE[x] input is HIGH, the associated
transmit or receive channel is configured for normal data transmission or reception. When
BISTLE returns LOW, the last values present on BOE[1:0] are captured in the internal BIST
Enable latch. The specific mapping of BOE[1:0] signals to transmit and receive BIST
enables is listed in Table 8. When the latch is closed, if the device is reset (TRSTZ is
sampled LOW), the latch is reset to disable BIST on both the transmit and receive channels.
Receive Channel Power-Control Latch Enable. Active HIGH. When RXLE = HIGH, the
signal on the BOE[0] input directly controls the power enable for the receive PLL and analog
logic. When the BOE[0] input is HIGH, the receive channel PLL and analog logic are active.
When the BOE[0] input is LOW, the receive channel PLL and analog logic are placed in a
non-functional power saving mode. When RXLE returns LOW, the last value present on
BOE[0] is captured in the internal RX PLL Enable latch. The specific mapping of BOE[1:0]
signals to the receive channel enable is listed in Table 8. When the latch is closed, if the
device is reset (TRSTZ is sampled LOW), the latch is reset to disable the receive channel.
BIST, Serial Output, and Receive Channel Enables. These inputs are passed to and
through the output enable latch when OELE = HIGH, and captured in this latch when OELE
returns LOW. These inputs are passed to and through the BIST enable latch when
BISTLE = HIGH, and captured in this latch when BISTLE returns LOW. These inputs are
passed to and through the Receive Channel enable latch when RXLE = HIGH, and captured
in this latch when RXLE returns LOW.
Link Fault Indication Output. Active LOW. LFI is the logical OR of four internal conditions:
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high for
> 5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset automat-
ically upon application of power to the device.
JTAG Test Clock.
Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not
selected.
Test Data In. JTAG data input port.
+3.3V power
Signal and power ground for all internal circuits
1. Received serial data frequency outside expected range
2. Analog amplitude below expected levels
3. Transition density lower than expected
4. Receive Channel disabled.
CYW15G0101DXB
CYV15G0101DXB
CYP15G0101DXB
Page 10 of 39
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