CYP15G0101DXB Cypress Semiconductor Corporation., CYP15G0101DXB Datasheet - Page 2

• Manufacturer Part Number: CYP15G0101DXB
• Description: Single-channel Hotlink Ii Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02031 Rev. *J
The CYW15G0101DXB
which includes operation at the OBSAI RP3 datarate of both
1536 MBaud and 768 MBaud.
The CYV15G0101DXB satisfies the SMPTE 259M and
SMPTE 292M compliance as per the EG34-1999 Pathological
Test Requirements. The transmit (TX) section of the
CYP(V)(W)15G0101DXB single-channel HOTLink II consists
of a byte-wide channel. The channel can accept either eight-bit
data
characters. Data characters are passed from the Transmit
Input Register to an embedded 8B/10B Encoder to improve
their serial transmission characteristics. These encoded
characters are then serialized and output from dual Positive
ECL (PECL)-compatible differential transmission-line drivers
at a bit-rate of either 10 or 20 times the input reference clock.
The receive (RX) section of the CYP(V)(W)15G0101DXB
Single-channel HOTLink II consists of a byte-wide channel.
The channel accepts a serial bit-stream from one of two
PECL-compatible differential Line Receivers and, using a
completely integrated PLL Clock Synchronizer, recovers the
timing information necessary for data reconstruction. The
recovered bit-stream is deserialized and framed into
characters, 8B/10B decoded, and checked for transmission
errors. Recovered decoded characters are then written to an
internal Elasticity Buffer, and presented to the destination host
system. The integrated 8B/10B Encoder/Decoder may be
bypassed for systems that present externally encoded or
scrambled data at the parallel interface.
Transceiver Logic Block Diagram
characters
or
[1]
pre-encoded
operates from 195 to 1540 MBaud,
10-bit
transmission
Encoder
8B/10B
Serializer
Phase
Buffer
Align
TX
x10
Elasticity
Deserializer
Decoder
The parallel I/O interface may be configured for numerous
forms of clocking to provide the highest flexibility in system
architecture. In addition to clocking the transmit path interfaces
from one or multiple sources, the receive interface may be
configured to present data relative to a recovered clock or to a
local reference clock.
The transmit and the receive channels contain BIST pattern
generators and checkers, respectively. This BIST hardware
allows at-speed testing of the high-speed serial data paths in
both transmit and receive sections, as well as across the inter-
connecting links.
HOTLink II devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed,
point-to-point
interconnecting
base-stations, servers and video transmission systems.
The CYV15G0101DXB is verified by testing to be compliant to
all the pathological test patterns documented in SMPTE
EG34-1999, for both the SMPTE 259M and 292M signaling
rates. The tests ensure that the receiver recovers data with no
errors for the following patterns:
8B/10B
1. Repetitions of 20 ones and 20 zeros.
2. Single burst of 44 ones or 44 zeros.
3. Repetitions of 19 ones followed by 1 zero or 19 zeros fol-
Buffer
Framer
RX
x11
lowed by 1 one.
serial
backplanes
links.
CYW15G0101DXB
CYV15G0101DXB
CYP15G0101DXB
Some
on
applications
switches,
Page 2 of 39
routers,
include
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