CYP15G0101DXB Cypress Semiconductor Corporation., CYP15G0101DXB Datasheet - Page 20

• Manufacturer Part Number: CYP15G0101DXB
• Description: Single-channel Hotlink Ii Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02031 Rev. *J
The COMDET output is HIGH when the character in the
Output Register contains the selected framing character at the
proper character boundary, and LOW for all other bit combina-
tions.
When the Low-Latency Framer and half-rate receive port
clocking is also enabled (RFMODE = LOW, RXRATE = HIGH,
and RXCKSEL = MID), the Framer will stretch the recovered
clock to the nearest 20-bit boundary such that the rising edge
of RXCLK+ occurs when COMDET = HIGH in the Output
Register.
When the Cypress or Alternate-mode Framer is enabled and
half-rate receive port clocking is also enabled (RFMODE ≠
LOW and RXRATE = HIGH), the output clock is not modified
when framing is detected, but a single pipeline stage may be
added or subtracted from the data stream by the Framer logic
such that the rising edge of RXCLK+ occurs when
COMDET = HIGH in the Output Register. This adjustment
only occurs when the Framer is enabled (RFEN = HIGH).
When the Framer is disabled, the clock boundaries are not
adjusted, and COMDET may be asserted during the rising
edge of RXCLK– (if an odd number of characters were
received following the initial framing).
Parity Generation
In addition to the eleven data and status bits that are
presented, an RXOP parity output is also available. This
allows the CYP(V)(W)15G0101DXB to support ODD parity
generation. To handle a wide range of system environments,
the CYP(V)(W)15G0101DXB supports different forms of parity
generation (in addition to no parity). When the Decoder is
enabled (DECMODE ≠ LOW), parity can be generated on
When the Decoder is bypassed (DECMODE = LOW), parity
can be generated on
These modes differ in the number of bits which are included in
the parity calculation. For all cases, only ODD parity is
provided which ensures that at least one bit of the data bus is
always a logic-1. Those bits covered by parity generation are
listed in Table 15.
Parity generation is enabled through the 3-level select
PARCTL input. When PARCTL = LOW, parity checking is
disabled, and the RXOP output is disabled (High-Z).
When PARCTL = MID (open) and the Decoder is enabled
(DECMODE ≠ LOW), ODD parity is generated for the received
and decoded character in the RXD[7:0] signals and is
presented on the RXOP output.
When PARCTL = MID (open) and the Decoder is bypassed
(DECMODE = LOW), ODD parity is generated for the received
and decoded character in the RXD[7:0] and RXST[1:0] bit
positions.
Notes:
16. Receive path parity output driver (RXOP) is disabled (High-Z) when PARCTL
17. When the Decoder is bypassed (DECMODE = LOW) and BIST is not enabled (Receive BIST Latch output is HIGH), RXST[2] is driven to a logic-0, except when
• the RXD[7:0] character
• the RXD[7:0] character and RXST[2:0] status.
• the RXD[7:0] and RXST[1:0] bits
• the RXD[7:0] and RXST[2:0] bits.
the character in the output buffer is a framing character.
=
Table 15. Output Register Parity Generation
When PARCTL = HIGH, ODD parity is generated for the
TXD[7:0] and the RXST[2:0] status bits.
Receive Status Bits
When the 10B/8B Decoder is enabled (DECMODE ≠ LOW),
each character presented at the Output Register includes
three associated status bits. These bits are used to identify
These conditions normally overlap; e.g., a valid data character
received with incorrect running disparity is not reported as a
valid data character. It is instead reported as a Decoder
violation of some specific type. This implies a hierarchy or
priority level to the various status bit combinations. The
hierarchy and value of each status is listed in Table 16.
Within these status decodes, there are three forms of status
reporting. The two normal or data status reporting modes
(Type A and Type B) are selectable through the RXMODE
input. These status types allow compatibility with legacy
systems, while allowing full reporting in new systems. The third
status type is used for reporting receive BIST status and
progress.
BIST Status State Machine
When the receive path is enabled to look for and compare the
received data stream with the BIST pattern, the RXST[2:0] bits
identify the present state of the BIST compare operation.
LOW.
• if the contents of the data bus are valid
• the type of character present
• the state of receive BIST operations (regardless of the state
• character violations.
RXST[2]
RXST[1]
RXST[0]
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
RXD[5]
RXD[6]
RXD[7]
Signal
Name
of DECMODE)
LOW
Receive Parity Generate Mode (PARCTL)
[16]
DECMODE
= LOW
CYW15G0101DXB
X
X
X
X
X
X
X
X
X
X
CYV15G0101DXB
CYP15G0101DXB
MID
DECMODE
≠ LOW
X
X
X
X
X
X
X
X
Page 20 of 39
HIGH
X
[17]
X
X
X
X
X
X
X
X
X
X
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