CYP15G0101DXB Cypress Semiconductor Corporation., CYP15G0101DXB Datasheet - Page 11

• Manufacturer Part Number: CYP15G0101DXB
• Description: Single-channel Hotlink Ii Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02031 Rev. *J
CYP(V)(W)15G0101DXB HOTLink II Operation
The CYP(V)(W)15G0101DXB is a highly configurable device
designed to support reliable transfer of large quantities of data
using high-speed serial links from a single source to one or
more destinations.
CYP(V)(W)15G0101DXB Transmit Data Path
Operating Modes
The transmit path of the CYP(V)(W)15G0101DXB supports a
single character-wide data path. This data path is used in
multiple operating modes as controlled by the TXMODE[1:0]
inputs.
Input Register
The bits in the Input Register support different assignments,
based on if the character is unencoded, encoded with two
control bits, or encoded with three control bits. These assign-
ments are shown in Table 1.
Table 1. Input Register Bit Assignments
The Input Register captures a minimum of eight data bits and
two control bits on each input clock cycle. When the Encoder
is bypassed, the TXCT[1:0] control bits are part of the
pre-encoded 10-bit data character.
When the Encoder is enabled (TXMODE[1] ≠ LOW), the
TXCT[1:0] bits are interpreted along with the TXD[7:0]
character to generate the specific 10-bit transmission
character. When TXMODE[0] ≠ HIGH, an additional special
character select (SCSEL) input is also captured and inter-
preted. This SCSEL input is used to modify the encoding of the
characters.
Phase-Align Buffer
Data from the Input Register is passed either to the Encoder
or to the Phase-Align buffer. When the transmit path is
Notes:
5.
6.
TXCT[1]
Signal Name
TXD[0]
The TXOP input is also captured in the Input Register, but its interpretation is under the separate control of PARCTL.
One or more K28.5 characters may be added or lost from the data stream during this reset operation. When used with non-Cypress devices that require a
complete 16-character Word Sync Sequence for proper receive Elasticity Buffer alignment, it is recommend that the sequence be followed by a second Word
Sync Sequence to ensure proper operation.
TXCT[0]
SCSEL
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD[6]
TXD[7]
TXD5]
(LSB)
(MSB)
Unencoded
Bypassed)
(Encoder
DIN[0]
DIN[1]
DIN[2]
DIN[3]
DIN[4]
DIN[5]
DIN[6]
DIN[7]
DIN[8]
DIN[9]
N/A
TXCT[0]
TXCT[1]
Control
Two-bit
TXD[0]
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD[5]
TXD[6]
TXD[7]
(Encoder Enabled)
N/A
[5]
Encoded
Three-bit
TXCT[0]
TXCT[1]
Control
SCSEL
TXD[0]
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD[5]
TXD[6]
TXD[7]
operated synchronous to REFCLK↑ (TXCKSEL = LOW and
TXRATE = LOW), the Phase-Align Buffer is bypassed and
data is passed directly to the Parity Check and Encoder block
to reduce latency.
When an Input Register clock with an uncontrolled phase
relationship to REFCLK is selected (TXCKSEL ≠ LOW) or if
data
(TXRATE = HIGH), the Phase-Align Buffer is enabled. This
buffer is used to absorb clock phase differences between the
presently selected input clock and the internal character clock.
Initialization of the Phase-Align Buffer takes place when the
TXRST input is sampled LOW by two consecutive rising edges
of REFCLK. When TXRST is returned HIGH, the present input
clock phase relative to REFCLK↑ is set. TXRST is an
asynchronous input, but is sampled internally to synchronize
it to the internal transmit path state machine.
Once set, the input clock is allowed to skew in time up to half
a character period in either direction relative to REFCLK↑;
i.e., ±180°. This time shift allows the delay path of the
character clock (relative to REFLCK↑) to change due to
operating voltage and temperature, while not affecting the
design operation.
If the phase offset, between the initialized location of the input
clock and REFCLK↑, exceeds the skew handling capabilities
of the Phase-Align Buffer, an error is reported on the TXPER
output. This output indicates a continuous error until the
Phase-Align Buffer is reset. While the error remains active, the
transmitter outputs a continuous C0.7 character to indicate to
the remote receiver that an error condition is present in the
link.
In specific transmit modes, it is also possible to reset the
Phase-Align Buffer with minimal disruption of the serial data
stream. When the transmit interface is configured for gener-
ation of atomic Word Sync Sequences (TXMODE[1] = MID)
and a Phase-Align Buffer error is present, the transmission of
a Word Sync Sequence will recenter the Phase-Align Buffer
and clear the error condition.
Parity Support
In addition to the ten data and control bits that are captured at
the transmit Input Register, a TXOP input is also available.
This allows the CYP(V)(W)15G0101DXB to support ODD
parity checking. Parity checking is available for all operating
modes (including Encoder Bypass). The specific mode of
parity checking is controlled by the PARCTL input, and
operates per Table 2.
When PARCTL = MID (open) and the Encoder is enabled
(TXMODE[1] ≠ LOW), only the TXD[7:0] data bits are checked
for
PARCTL = HIGH with the Encoder enabled (or MID with the
Encoder bypassed), the TXD[7:0] and TXCT[1:0] inputs are
checked for ODD parity along with the TXOP bit. When
PARCTL = LOW, parity checking is disabled.
ODD
is
captured
parity
along
on
[6]
with
CYW15G0101DXB
both
CYV15G0101DXB
CYP15G0101DXB
the
edges
TXOP
Page 11 of 39
of
bit.
REFCLK
When
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