CYP15G0101DXB Cypress Semiconductor Corporation., CYP15G0101DXB Datasheet - Page 25

• Manufacturer Part Number: CYP15G0101DXB
• Description: Single-channel Hotlink Ii Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02031 Rev. *J
CYP(V)(W)15G0101DXB AC Characteristics
t
t
t
f
t
t
t
Receiver LVTTL Switching Characteristics
f
t
t
t
t
t
t
t
t
REFCLK Switching Characteristics Over the Operating Range
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
32. Parallel data output specifications are only valid if all inputs or outputs are loaded with similar DC and AC loads.
33. The duty cycle specification is a simultaneous condition with the t
34. Since this timing parameter is greater than the minimum time period of REFCLK it sets an upper limit to the frequency in which REFCLKx can be used to clock
TXCLKF
TXDS
TXDH
TOS
TXCLKO
TXCLKOD+
TXCLKOD–
RS
RXCLKP
RXCLKH
RXCLKL
RXCLKD
RXCLKR
RXCLKF
RXDV–
RXDV+
REF
REFCLK
REFH
REFL
REFD
REFR
REFF
TREFDS
TREFDH
RREFDA
RREFDV
REFDV–
REFDV+
REFCDV–
REFCDV+
REFRX
Parameter
cannot be as large as 30%–70%.
the receive data out of the output register. For predictable timing, users can use this parameter only if REFCLK period is greater than sum of t
time of the upstream device. When this condition is not true, RXCLKC± or RXCLKA± (a buffered or delayed version of REFCLK when RXCKSELx = LOW) could
be used to clock the receive data out of the device.
[29, 30, 31]
[33]
[29, 30, 31]
[10, 29]
[32]
[32]
[29]
[29]
[29, 30, 31]
[34]
TXCLK Fall Time
Transmit Data Set-Up Time to TXCLK↑ (TXCKSEL ≠ LOW)
Transmit Data Hold Time from TXCLK↑ (TXCKSEL ≠ LOW)
TXCLKO Clock Frequency = 1x or 2x REFCLK Frequency
TXCLKO Period
TXCLKO+ Duty Cycle with 60% HIGH time
TXCLKO– Duty Cycle with 40% HIGH time
RXCLK Clock Output Frequency
RXCLK Period
RXCLK HIGH Time (RXRATE = LOW)
RXCLK HIGH Time (RXRATE = HIGH)
RXCLK LOW Time (RXRATE = LOW)
RXCLK LOW Time (RXRATE = HIGH)
RXCLK Duty Cycle centered at 50%
RXCLK Rise Time
RXCLK Fall Time
Status and Data Valid Time to RXCLK (RXCKSEL = MID)
Status and Data Valid Time to RXCLK (HALF RATE RECOVERED CLOCK)
Status and Data Valid Time From RXCLK (RXCKSEL = MID)
Status and Data Valid Time From RXCLK (HALF RATE RECOVERED CLOCK) 5UI – 2.3
REFCLK Clock Frequency
REFCLK Period
REFCLK HIGH Time (TXRATE = HIGH)
REFCLK HIGH Time (TXRATE = LOW)
REFCLK LOW Time (TXRATE = HIGH)
REFCLK LOW Time (TXRATE = LOW)
REFCLK Duty Cycle
REFCLK Rise Time (20% – 80%)
REFCLK Fall Time (20% – 80%)
Transmit Data Setup Time to REFCLK (TXCKSEL = LOW)
Transmit Data Hold Time from REFCLK (TXCKSEL = LOW)
Receive Data Access Time from REFCLK (RXCKSEL = LOW)
Receive Data Valid Time from REFCLK (RXCKSEL = LOW)
Received Data Valid Time to RXCLK (RXCKSEL = LOW)
Received Data Valid Time from RXCLK (RXCKSEL = LOW)
Received Data Valid Time to RXCLKC (RXCKSEL = LOW)
Received Data Valid Time from RXCLKC (RXCKSEL = LOW)
REFCLK Frequency Referenced to Extracted Received Clock Frequency
Description
REFH
Over the Operating Range (continued)
and t
REFL
parameters. This means that at faster character rates the REFCLK duty cycle
CYW15G0101DXB
CYV15G0101DXB
CYP15G0101DXB
10UI – 4.7
10UI – 4.3
5UI – 1.5
5UI – 1.0
5UI – 1.8
2.33
2.33
6.66
6.66
–1500
6.6
2.9
2.9
Min.
19.5
–1.0
–0.5
9.75
5.66
5.66
–1.0
19.5
–0.2
0.2
1.7
0.8
0.3
0.3
5.9
5.9
1.7
0.8
2.5
0.5
30
[28]
[29]
[29]
[28]
[28]
[29]
[29]
102.56
150
150
150
+1500
51.28
26.64
52.28
26.64
52.28
51.28
Max.
+0.5
+1.0
+1.0
RREFDA
Page 25 of 39
1.7
1.2
1.2
9.5
70
2
2
[27]
[27]
[27]
and set-up
MHz
MHz
MHz
Unit
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
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