CYP15G0101DXB Cypress Semiconductor Corporation., CYP15G0101DXB Datasheet - Page 15

• Manufacturer Part Number: CYP15G0101DXB
• Description: Single-channel Hotlink Ii Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02031 Rev. *J
dissipation. If both Serial Drivers for the channel are disabled,
the internal logic for the transmit channel is also configured for
lowest power operation. When OELE returns LOW, the values
present on the BOE[1:0] inputs are latched in the Output
Enable Latch, and remain there until OELE returns HIGH to
open the latch again. A device reset (TRSTZ sampled LOW)
clears this latch and disables both Serial Drivers.
Note. When both serial output drivers are disabled and a
driver is re-enabled, the data on the Serial Drivers may not
meet all timing specifications for up to 200 µs.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a character-rate or
half-character-rate external clock at the REFCLK input, and
multiples that clock by 10 or 20 (as selected by TXRATE) to
generate a bit-rate clock for use by the Transmit Shifter. It also
provides a character-rate clock used by the transmit path.
This clock multiplier PLL can accept a REFCLK input between
19.5 MHz and 150 MHz (19.5 MHz and 154 MHz for
CYW15G0101DXB), however, this clock range is limited by
the operating mode of the CYP(V)(W)15G0101DXB clock
multiplier (controlled by TXRATE) and by the level on the
SPDSEL input.
When TXRATE=HIGH, configuring TXCKSEL = HIGH or MID
is an invalid mode of operation.
SPDSEL is a 3-level select
of three operating ranges for the serial data outputs and inputs.
The operating serial signaling-rate and allowable range of
REFCLK frequencies are listed in Table 9.
Table 9. Operating Speed Settings
The REFCLK± input is a differential input with each input inter-
nally biased to 1.4V. If the REFCLK+ input is connected to a
TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point.
When both the REFCLK+ and REFCLK− inputs are
connected, the clock source must be a differential clock. This
can be either a differential LVPECL clock that is DC- or
AC-coupled, or a differential LVTTL or LVCMOS clock.
By connecting the REFCLK− input to an external voltage
source or resistive voltage divider, it is possible to adjust the
Note:
10. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. REFCLK
MID (Open)
SPDSEL
must be within ±1500 PPM (±0.15%) of the remote transmitter’s PLL reference (REFCLK) frequency. Although transmitting to a HOTLink II receiver necessitates
the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be within the limits
specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z Gigabit Ethernet
compliant, the frequency stability of the crystal needs to be within ±100 PPM.
HIGH
LOW
TXRATE
1
0
1
0
1
0
[4]
(ternary) input that selects one
Frequency
REFCLK
reserved
19.5–40
80–150
20–40
40–75
(MHz)
40–80
Rate (MBaud)
CYW15G0101
(800–1540 for
Signaling
800–1500
195–400
400–800
DXB)
reference point of the REFCLK+ input for alternate logic levels.
When doing so, it is necessary to ensure that the 0V-differ-
ential crossing point remains within the parametric range
supported by the input.
CYP(V)(W)15G0101DXB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, IN1± and IN2±, are available
for accepting serial data streams. The active Serial Line
Receiver is selected using the INSEL input. Both Serial Line
Receivers have differential inputs, and can accommodate wire
interconnect and filtering losses or transmission line attenu-
ation greater than 16 dB. For normal operation, these inputs
should receive a signal of at least V
peak-to-peak differential. Each Line Receiver can be DC- or
AC-coupled to +3.3V powered fiber-optic interface modules
(any ECL/PECL logic family, not limited to 100K PECL) or
AC-coupled to +5V-powered optical modules. The common-
mode tolerance of the receivers accommodates a wide range
of signal termination voltages. Each receiver provides internal
DC-restoration, to the center of the receiver’s common mode
range, for AC-coupled signals.
The local loop-back input (LPEN) allows the serial transmit
data to be routed internally back to the Clock and Data
Recovery circuit. When configured for local loop-back, the
transmit Serial Driver outputs are forced to output a differential
logic-1. This prevents local diagnostic patterns from being
broadcast to attached remote receivers.
Signal Detect/Link Fault
Each selected Line Receiver (i.e., that routed to the Clock and
Data Recovery PLL) is simultaneously monitored for
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFI (Link Fault Indicator) output.
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable to allow
operation with highly attenuated signals, or in high-noise
environments. This adjustment is made through the SDASEL
signal, a 3-level select
point for the detection of a valid signal at one of three levels,
as listed in Table 10.
The Analog Signal Detect monitor is active for the present Line
Receiver, as selected by the INSEL input. When configured for
local loop-back (LPEN = HIGH), the Analog Signal Detect
Monitor is disabled.
• analog amplitude above limit specified by SDASEL
• transition density greater than specified limit
• range controller reports the received data stream within
• receive channel enabled.
normal frequency range (±1500 ppm)
[4]
(ternary) input, which sets the trip
CYW15G0101DXB
CYV15G0101DXB
CYP15G0101DXB
DIFFS
> 100 mV, or 200-mV
[10]
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