CYP15G0101DXB Cypress Semiconductor Corporation., CYP15G0101DXB Datasheet - Page 17

• Manufacturer Part Number: CYP15G0101DXB
• Description: Single-channel Hotlink Ii Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02031 Rev. *J
Framing Character
The CYP(V)(W)15G0101DXB allows selection of two combi-
nations of framing characters to support requirements of
different interfaces. The selection of the framing character is
made through the FRAMCHAR input.
The specific bit combinations of these framing characters are
listed in Table 11. When the specific bit combination of the
selected framing character is detected by the Framer, the
boundaries of the characters present in the received data
stream are known.
Table 11. Framing Character Selector
Framer
The Framer operates in one of three different modes, as
selected by the RFMODE input. In addition, the Framer itself
may be enabled or disabled through the RFEN input. When
RFEN = LOW, the Framer is disabled, and no combination of
bits in a received data stream will alter the character bound-
aries. When RFEN = HIGH, the Framer-mode selected by
RFMODE is enabled.
When RFMODE = LOW, the Low-latency Framer is selected.
This Framer operates by stretching the recovered character
clock until it aligns with the received character boundaries. In
this mode, the Framer starts its alignment process on the first
detection of the selected framing character. To reduce the
impact on external circuits that make use of a recovered clock,
the clock period is not stretched by more than two bit-periods
in any one clock cycle. When operated with a character-rate
output clock (RXRATE = LOW), the output of properly framed
characters may be delayed by up to nine character-clock
cycles from the detection of the selected framing character.
When operated with a half-character-rate output clock
(RXRATE = HIGH), the output of properly framed characters
may be delayed by up to 14 character-clock cycles from the
detection of the selected framing character.
When RFMODE = MID (open), the Cypress-mode Multi-Byte
Framer is selected. The required detection of multiple framing
characters makes the link much more robust to incorrect
framing due to aliased framing characters in the data stream.
In this mode, the Framer does not adjust the character clock
boundary, but instead aligns the character to the already
recovered character clock. This ensures that the recovered
clock does not contain any significant phase changes or hops
during normal operation or framing, and allows the recovered
clock to be replicated and distributed to other external circuits
or components using PLL-based clock distribution elements.
In this framing mode, the character boundaries are only
Notes:
13. The standard definition of a Comma contains only seven bits. However, since all valid Comma characters within the 8B/10B character set also have the 8th bit
14. When Receive BIST is enabled on a channel, the Low-Latency Framer must not be enabled. The BIST sequence contains an aliased K28.5 framing character,
FRAMCHAR
MID (Open)
as an inversion of the 7th bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.
which would cause the Receiver to update its character boundaries incorrectly.
HIGH
LOW
Character Name
Comma+
Comma–
–K28.5
+K28.5
Bits Detected in Framer
Reserved for test
00111110XX
or 11000001XX
[14]
Bits Detected
0011111010 or
1100000101
[13]
adjusted if the selected framing character is detected at least
twice within a span of 50 bits, with both instances on identical
10-bit character boundaries.
When RFMODE = HIGH, the Alternate-mode Multi-Byte
Framer is enabled. Like the Cypress-mode Multi-Byte Framer,
multiple framing characters must be detected before the
character boundary is adjusted. In this mode, the Framer does
not adjust the character clock boundary, but instead aligns the
character to the already recovered character clock. In this
mode, the data stream must contain a minimum of four of the
selected framing characters, received as consecutive
characters, on identical 10-bit boundaries, before character
framing is adjusted.
Framing is enabled when RFEN = HIGH. If RFEN = LOW, the
Framer is disabled. When the Framer is disabled, no changes
are made to the recovered character boundary, regardless of
the presence of framing characters in the data stream.
10B/8B Decoder Block
The Decoder logic block performs three primary functions:
10B/8B Decoder
The framed parallel output of the Deserializer Shifter is passed
to the 10B/8B Decoder where, if the Decoder is enabled
(DECMODE ≠ LOW), it is transformed from a 10-bit trans-
mission character back to the original Data and Special
Character codes. This block uses the 10B/8B Decoder
patterns in Table 20 and Table 21 of this data sheet. Valid data
characters are indicated by a 000b bit-combination on the
RXST[2:0] status bits, and Special Character codes are
indicated by a 001b bit-combination on these same status
outputs. Framing characters, invalid patterns, disparity errors,
and synchronization status are presented as alternate combi-
nations of these status bits.
The 10B/8B Decoder operates in two normal modes, and can
also be bypassed. The operating mode for the Decoder is
controlled by the DECMODE input.
When DECMODE = LOW, the Decoder is bypassed and raw
10-bit characters are passed to the Output Register. In this
mode, the receive Elasticity Buffers are bypassed, and
RXCKSEL must be MID.
When DECMODE = MID (or open), the 10-bit transmission
characters are decoded using Table 20 and Table 21.
Received Special Code characters are decoded using the
Cypress column of Table 21.
When DECMODE = HIGH, the 10-bit transmission characters
are decoded using Table 20 and Table 21. Received Special
Code characters are decoded using the Alternate column of
Table 21.
• decoding the received transmission characters back into
• comparing generated BIST patterns with received
• generation of ODD parity on the decoded characters.
Data and Special Character codes
characters to permit at-speed link and device testing
CYW15G0101DXB
CYV15G0101DXB
CYP15G0101DXB
Page 17 of 39
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