CYP15G0101DXB Cypress Semiconductor Corporation., CYP15G0101DXB Datasheet - Page 18

• Manufacturer Part Number: CYP15G0101DXB
• Description: Single-channel Hotlink Ii Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02031 Rev. *J
Receive BIST Operation
The Receiver interface contains an internal pattern generator
that can be used to validate both device and link operation.
This generator is enabled by the BOE[0] signal as listed in
Table 8 (when the BISTLE latch enable input is HIGH). When
enabled, a register in the Receive channel becomes a pattern
generator and checker by logically converting to a Linear
Feedback Shift Register (LFSR). This LFSR generates a
511-character sequence that includes all Data and Special
Character codes, including the explicit violation symbols. This
provides a predictable yet pseudo-random sequence that can
be matched to an identical LFSR in the attached Transmitter.
If the receive channels are configured for REFCLK clocking
(RXCKSEL = LOW), each pass is preceded by a 16-character
Word Sync Sequence.
When synchronized with the received data stream, the
Receiver checks each character in the Decoder with each
character generated by the LFSR and indicates compare
errors and BIST status at the RXST[2:0] bits of the Output
Register.
When the BISTLE signal is HIGH, if the BOE[0] input is LOW
the BIST generator/checker in the Receive channel is enabled
(and if BOE[1] = LOW the BIST generator in the transmit
channel is enabled). When BISTLE returns LOW, the values
of the BOE[1:0] signals are captured in the BIST Enable Latch.
These values remain in the BIST Enable Latch until BISTLE is
returned high to open the latch again. All captured signals in
the BIST Enable Latch are set HIGH (i.e., BIST is disabled)
following a device reset (TRSTZ is sampled LOW).
When BIST is first recognized as being enabled in the
Receiver, the LFSR is preset to the BIST-loop start-code of
D0.0. This D0.0 character is sent only once per BIST loop. The
status of the BIST progress and any character mismatches is
presented on the RXST[2:0] status outputs.
Code rule violations or running disparity errors that occur as
part of the BIST loop do not cause an error indication.
RXST[2:0] indicates 010b or 100b for one character period per
BIST loop to indicate loop completion. This status can be used
to check test pattern progress. These same status values are
presented when the Decoder is bypassed and BIST is enabled
on the Receive channel.
The status reported on RXST[2:0] by the BIST state machine
are listed in Table 16. When Receive BIST is enabled, the
same status is reported on the receive status outputs
regardless of the state of DECMODE.
The specific patterns checked by each receiver are described
in detail in the Cypress application note “HOTLink Built-In
Self-test.”
CYP(V)(W)15G0101DXB is identical to that in the CY7B933
and CY7C924DX, allowing interoperable systems to be built
when used at compatible serial signaling rates.
If the number of invalid characters received ever exceeds the
number of valid characters by 16, the receive BIST state
machine aborts the compare operations and resets the LFSR
to the D0.0 state to look for the start of the BIST sequence
again.
When the receive paths are configured for REFCLK clocking
(RXCKSEL = LOW), each pass must be preceded by a
16-character Word Sync Sequence to allow output buffer
alignment and management of clock frequency variations.
The
sequence
compared
by
the
This is automatically generated by the transmitter when its
local RXCKSEL = LOW.
The BIST state machine requires the characters to be correctly
framed for it to detect the BIST sequence. If the Low-Latency
Framer is enabled (RFMODE = LOW), the Framer will
misalign to an aliased framing character within the BIST
sequence. If the Alternate-mode Multi-Byte Framer is enabled
(RFMODE = HIGH) and the Receiver outputs are clocked
relative to a recovered clock (RXCKSEL = MID), it is
necessary to frame the Receiver before BIST is enabled. If the
Receiver
(RXCKSEL = LOW), the transmitter precedes every 511
character BIST sequence with a 16-character Word Sync
Sequence.
Receive Elasticity Buffer
The receive channel contains an Elasticity Buffer that is
designed to support multiple clocking modes. This buffer
allows data to be read using an Elasticity Buffer read-clock that
is asynchronous in both frequency and phase from the
Elasticity Buffer write clock, or to use a read clock that is
frequency coherent but with uncontrolled phase relative to the
Elasticity Buffer write clock.
The Elasticity Buffer is 10 characters deep, and supports a
12-bit-wide data path. It is capable of supporting a decoded
character, three status bits, and a parity bit for each character
present in the buffer. The write clock for this buffer is always
the recovered clock for the read channel.
The read clock for the Elasticity Buffer can be set to
character-rate REFCLK (RXCKSEL = LOW and DECMODE ≠
LOW). The write clock for the Elasticity Buffer is always
recovered clock.
When RXCKSEL = LOW, the Receive channel is clocked by
REFCLK. The RXCLK± and RXCLKC+ outputs present
buffered and delayed forms of REFCLK. In this mode, the
receive Elasticity Buffer is enabled. For REFCLK clocking, the
Elasticity Buffer must be able to insert K28.5 characters and
delete framing characters as appropriate. The Elasticity Buffer
is bypassed whenever the Decoder is bypassed (DECMODE
= LOW). When the Decoder and Elasticity Buffer are
bypassed, RXCKSELx must be set to MID. When
RXCKSEL = MID (or open), the receive channel Output
Register is clocked by the recovered clock.
The insertion of a K28.5 or deletion of a framing character can
occur at any time. However, the actual timing on these inser-
tions and deletions is controlled in part by the how the trans-
mitter sends its data. Insertion of a K28.5 character can only
occur when the receiver has a framing character in the
Elasticity Buffer. Likewise, to delete a framing character, one
must also be present in the Elasticity Buffer. To prevent an
Elasticity Buffer overflow or underflow in the receive channel,
a minimum density of framing characters must be present in
the received data stream.
Prior to reception of valid data, at least one Word Sync
Sequence (or at least four framing characters) must be
received to allow the receive Elasticity Buffer to be centered.
The Elasticity Buffer may also be centered by a device reset
operation initiated through the TRSTZ input. However,
following such an event, the CYP(V)(W)15G0101DXB will
normally require a framing event before it will correctly decode
characters.
outputs
are
clocked
CYW15G0101DXB
CYV15G0101DXB
CYP15G0101DXB
relative
Page 18 of 39
to
REFCLK
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