CYP15G0101DXB Cypress Semiconductor Corporation., CYP15G0101DXB Datasheet - Page 16

• Manufacturer Part Number: CYP15G0101DXB
• Description: Single-channel Hotlink Ii Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02031 Rev. *J
Transition Density
The Transition Detection logic checks for the absence of any
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received
(within the referenced period), the Transition Detection logic
asserts LFI. The LFI output remains asserted until at least one
transition is detected in each of three adjacent received
characters.
Table 10. Analog Amplitude Detect Valid Signal Levels
Range Control
The Clock/Data Recovery (CDR) circuit includes logic to
monitor the frequency of the phase-locked loop (PLL) Voltage
Controlled Oscillator (VCO) used to sample the incoming data
stream. This logic ensures that the VCO operates at, or near
the rate of the incoming data stream for two primary cases:
To perform this function, the frequency of the VCO is periodi-
cally sampled and compared to the frequency of the REFCLK
input. If the VCO is running at a frequency beyond
+1500ppm
is periodically forced to the correct frequency (as defined by
REFCLK, SPDSEL, and TXRATE) and then released in an
attempt to lock to the input data stream. The sampling and
relock period of the Range Control is calculated as follows:
RANGE CONTROL SAMPLING PERIOD = (REFCLK-
PERIOD) * (16000).
During the time that the Range Control forces the PLL VCO to
run at REFCLK*10 (or REFCLK*20 when TXRATE = HIGH)
rate, the LFIx output will be asserted LOW. While the PLL is
attempting to re-lock to the incoming data stream, LFIx may be
either HIGH or LOW (depending on other factors such as
transition density and amplitude detection) and the recovered
byte clock (RXCLK) may run at an incorrect rate (depending
on the quality or existence of the input serial data stream).
After a valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx should be
HIGH.
Receive Channel Enabled
The CYP(V)(W)15G0101DXB receive channel can be
enabled and disabled through the BOE[0] input, as controlled
by the RXLE latch-enable signal. When RXLE = HIGH, the
signal present on the BOE[0] input is passed through the
Receive Channel Enable Latch to control the PLL and logic of
the receive channel. The BOE[1:0] input functions are listed in
Table 8.
Notes:
11. The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals
12. When a disabled receive channel is reenabled, the status of the LFI output and data on the parallel outputs may be indeterminate for up to 2 ms.
• when the incoming data stream resumes after a time in
• when the incoming data stream is outside the acceptable
MID (Open) 280-mV p-p differential
SDASEL
which it has been “missing.”
frequency range.
may have a sign-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
HIGH
LOW
[10]
as defined by the reference clock frequency, it
140-mV p-p differential
420-mV p-p differential
Typical Signal with Peak Amplitudes
Above
[11]
When RXLE = HIGH and BOE[0] = HIGH, the receive channel
is enabled to receive and recover a serial stream from the Line
Receiver. When RXLE = HIGH and BOE[0] = LOW, the
receive channel is disabled and internally configured for
minimum power dissipation. When disabled, the channel
indicates a constant LFI output. When RXLE returns LOW, the
values present on the BOE[1:0] inputs are latched in the
Receive Channel Enable Latch, and remain there until RXLE
returns HIGH to open the latch again.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from a
received serial stream is performed by a CDR block within the
receive channel. The clock extraction function is performed by
a high-performance embedded PLL that tracks the frequency
of the transitions in the incoming bit stream and aligns the
phase of the internal bit-rate clock to the transitions in the
serial data stream.
The CDR accepts a character-rate (bit-rate ÷ 10) or
half-character-rate (bit-rate ÷ 20) reference clock from the
REFCLK input. This REFCLK input is used to
Regardless of the type of signal present, the CDR will attempt
to recover a data stream from it. If the frequency of the
recovered data stream is outside the limits of the range control
monitor, the CDR will switch to track REFCLK instead of the
data stream. Once the CDR output (RXCLK) frequency returns
back close to REFCLK frequency, the CDR input will be
switched back to track the input data stream. In case no data
is present at the input, this switching behavior may result in
brief RXCLK frequency excursions from REFCLK. However,
the validity of the input data stream is indicated by the LFIx
output. The frequency of REFCLK is required to be within
± 1500 ppm
REFCLK input of the remote transmitter to ensure a lock to the
incoming data stream.
For systems using multiple or redundant connections, the LFI
output can be used to select an alternate data stream. When
an LFI indication is detected, external logic can toggle
selection of the IN1± and IN2± inputs through the INSEL input.
When a port switch takes place, it is necessary for the receive
PLL to reacquire the new serial stream and frame to the
incoming character boundaries.
Deserializer/Framer
Each CDR circuit extracts bits from the serial data stream and
clocks these bits into the Shifter/Framer at the bit-clock rate.
When enabled, the Framer examines the data stream, looking
for one or more Comma or K28.5 characters at all possible bit
positions. The location of these characters in the data stream
are used to determine the character boundaries of all following
characters.
• ensure that the VCO (within the CDR) is operating at the
• reduce PLL acquisition time
• limit unlocked frequency excursions of the CDR VCO when
correct frequency
there is no input data present at the selected Serial Line
Receiver.
[10]
of the frequency of the clock that drives the
CYW15G0101DXB
CYV15G0101DXB
CYP15G0101DXB
[12]
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