BC41B143A-ANN-E4 ETC, BC41B143A-ANN-E4 Datasheet - Page 5

• Manufacturer Part Number: BC41B143A-ANN-E4
• Description: Bluecore 4-rom CSP EDR Single Chip Bluetooth v2.0 + EDR System
• Manufacturer: ETC

Contents
List of Figures
Figure 3.1: BlueCore4-ROM CSP Package ............................................................................................................ 9
Figure 7.1: BlueCore4-ROM CSP Device Diagram for CSP Package .................................................................. 38
Figure 9.1: BlueCore HCI Stack ............................................................................................................................ 42
Figure 10.1: Basic Data Rate and Enhanced Data Rate Packet Types ................................................................ 46
Figure 10.2: π/4 DQPSK Constellation Pattern ..................................................................................................... 47
Figure 10.3: 8DPSK Constellation Pattern ............................................................................................................ 48
Figure 11.1: Circuit RF_A and RF_B..................................................................................................................... 49
Figure 11.2: Internal Power Ramping.................................................................................................................... 50
Figure 11.3: TCXO Clock Accuracy ...................................................................................................................... 52
Figure 11.4: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting......................................... 53
Figure 11.5: Crystal Driver Circuit ......................................................................................................................... 54
Figure 11.6: Crystal Equivalent Circuit .................................................................................................................. 55
Figure 11.7: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency............................. 57
Figure 11.8: Crystal Driver Transconductance vs. Driver Level Register Setting .................................................. 58
Figure 11.9: Crystal Driver Negative Resistance as a Function of Drive Level Setting ......................................... 59
Figure 11.10: Break Signal.................................................................................................................................... 61
Figure 11.11: UART Bypass Architecture ............................................................................................................. 62
Figure 11.12: USB Connections for Self Powered Mode ...................................................................................... 64
Figure 11.13: USB Connections for Bus-Powered Mode ...................................................................................... 64
Figure 11.14: USB_DETACH and USB_WAKE_UP Signalling............................................................................. 65
Figure 11.15: Write Operation ............................................................................................................................... 67
Figure 11.16: Read Operation............................................................................................................................... 67
Figure 11.17: BlueCore4-ROM CSP as PCM Interface Master............................................................................. 68
Figure 11.18: BlueCore4-ROM CSP as PCM Interface Slave............................................................................... 69
Figure 11.19: Long Frame Sync (Shown with 8-bit Companded Sample)............................................................. 69
Figure 11.20: Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 69
Figure 11.21: Multi Slot Operation with Two Slots and 8-bit Companded Samples .............................................. 70
Figure 11.22: GCI Interface................................................................................................................................... 70
Figure 11.23: 16-Bit Slot Length and Sample Formats ......................................................................................... 71
Figure 11.24: PCM Master Timing Long Frame Sync ........................................................................................... 73
Figure 11.25: PCM Master Timing Short Frame Sync........................................................................................... 73
Figure 11.26: PCM Slave Timing Long Frame Sync ............................................................................................. 74
Figure 11.27: PCM Slave Timing Short Frame Sync............................................................................................. 75
Figure 11.28: Example EEPROM Connection ...................................................................................................... 78
Figure 11.29: Example TXCO Enable OR Function .............................................................................................. 78
Figure 12.1: Application Circuit for CSP Package ................................................................................................. 81
Figure 14.1: BlueCore4-ROM CSP Package Dimensions..................................................................................... 82
This material is subject to CSR’s non-disclosure agreement
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