BC41B143A-ANN-E4 ETC, BC41B143A-ANN-E4 Datasheet - Page 77

• Manufacturer Part Number: BC41B143A-ANN-E4
• Description: Bluecore 4-rom CSP EDR Single Chip Bluetooth v2.0 + EDR System
• Manufacturer: ETC

11.8
Thirteen lines of programmable bi-directional input/outputs (I/O) are provided. PIO[10:8] and PIO[3:0] are
powered from VDD_PIO. PIO[7:4] are powered from VDD_PADS. AIO[0] and AIO[2] are powered from
VDD_USB.
PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. All PIO lines
are configured as inputs with weak pull-downs at reset. See section 3 CSP Package Information for details.
PIO[0] and PIO[1] are normally dedicated to RXEN and TXEN respectively, but they are available for general
use.
Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. PIO[6] or
PIO[2] can be configured as a request line for an external clock source. This is useful when the clock to
BlueCore4-ROM CSP is provided from a system application specific integrated circuit (ASIC).
BlueCore4-ROM CSP has two general-purpose analogue interface pins, AIO[0] and AIO[2]. These access
internal circuitry and control signals. One pin, typically AIO[2], is allocated to decoupling for the on-chip band gap
reference voltage. The other can be configured to provide additional functionality.
Auxiliary functions available via these pins include an 8-bit ADC and an 8-bit DAC. Typically the ADC is used for
battery voltage measurement. Signals selectable at these pins include the band gap reference voltage and a
variety of clock signals, 48, 24, 16, 8MHz and the XTAL clock frequency. When used with analogue signals the
voltage range is constrained by the analogue supply voltage (1.8V). When configured to drive out digital level
signals (clocks) generated from within the analogue part of the device, the output voltage level is determined by
VDD_USB (1.8V).
11.8.1 PIO Defaults for BlueCore4-ROM CSP
CSR cannot guarantee that these terminal functions remain the same. Refer to the software release note for the
implementation of these PIO lines because they are firmware build specific.
BC41B143A-ds-002Pd
Name (Continued)
CNT_LIMIT
CNT_RATE
SYNC_LIMIT
I/O Parallel Ports
Table 11.12: PSKEY_PCM_LOW_JITTER_CONFIG Description
Bit Position
[12:0]
[23:16]
[31:24]
This material is subject to CSR’s non-disclosure agreement
© Cambridge Silicon Radio Limited 2005
Production Information
Description
Sets PCM_CLK counter limit.
Sets PCM_CLK count rate.
Sets PCM_SYNC division relative to PCM_CLK.
Device Terminal Descriptions
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