BC41B143A-ANN-E4 ETC, BC41B143A-ANN-E4 Datasheet - Page 66

• Manufacturer Part Number: BC41B143A-ANN-E4
• Description: Bluecore 4-rom CSP EDR Single Chip Bluetooth v2.0 + EDR System
• Manufacturer: ETC

11.5.9 USB Compliance
BlueCore4-ROM CSP is designed to be compatible with and adhere to the USB specification v1.1, details of
which are available from http://www.usb.org. The specification contains valuable information on aspects such as
PCB track impedance, supply inrush current and product labelling.
Although BlueCore4-ROM CSP meets the USB specification, CSR cannot guarantee that an application circuit
designed around the IC is USB compliant. The choice of application circuit, component choice and PCB layout all
affect USB signal quality and electrical characteristics. The information in this document is intended as a guide
and should be read in association with the USB specification, with particular attention being given to Chapter 7.
Independent USB qualification must be sought before an application is deemed USB compliant and can bear the
USB logo. Such qualification can be obtained from a USB plugfest or from an independent USB test house.
Terminals USB_DP and USB_DN adhere to the USB specification (Chapter 7) electrical requirements.
11.5.10 USB 2.0 Compatibility
BlueCore4-ROM CSP is compatible with USB 2.0 host controllers. Under these circumstances the two ends
default to 12Mbits/s and do not enter high-speed mode.
11.6
BlueCore4-ROM CSP uses a 16-bit data and 16-bit address serial peripheral interface. Transactions may occur
when the internal processor is running or is stopped. This section describes the considerations required when
interfacing to BlueCore4-ROM CSP via the four dedicated serial peripheral interface terminals. Data can be
written or read one word at a time or the auto increment feature can be used to access blocks of data.
11.6.1 Instruction Cycle
The BlueCore4-ROM CSP is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO.
The instruction cycle for an SPI transaction is shown in Table 11.8.
Except when resetting the SPI interface, SPI_CSB must be held low during the transaction. Data on SPI_MOSI is
clocked into the BlueCore4-ROM CSP on the rising edge of SPI_CLK. When reading, BlueCore4-ROM CSP
replies to the master on SPI_MISO with the data changing on the falling edge of the SPI_CLK. The master
provides the clock on SPI_CLK. The transaction is terminated by taking SPI_CSB high.
It is a significant overhead to send a command word and the address of a register every time the register is to be
read or written, especially when large amounts of data are transferred. To overcome this BlueCore4-ROM CSP
offers increased data transfer efficiency via an auto increment operation. To invoke auto increment, SPI_CSB is
kept low after a word of data is written or read, which auto increments the address, while providing an extra 16
clock cycles for each extra word to be written or read.
BC41B143A-ds-002Pd
1
2
3
4
5
Serial Peripheral Interface
Write the command word
Write or read data words
Reset the SPI interface
Write the address
Termination
Table 11.8: Instruction Cycle for an SPI Transaction
This material is subject to CSR’s non-disclosure agreement
© Cambridge Silicon Radio Limited 2005
Production Information
Take SPI_CSB low and clock in the 8-bit command
Hold SPI_CSB high for two SPI_CLK cycles
Clock in or out 16-bit data word(s)
Clock in the 16-bit address word
Take SPI_CSB high
Device Terminal Descriptions
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