BC41B143A-ANN-E4 ETC, BC41B143A-ANN-E4 Datasheet - Page 51

• Manufacturer Part Number: BC41B143A-ANN-E4
• Description: Bluecore 4-rom CSP EDR Single Chip Bluetooth v2.0 + EDR System
• Manufacturer: ETC

11.1.2 Control of External RF Components
A PS Key, PSKEY_TXRX_PIO_CONTROL, controls external RF components such as a switch, an external PA
or an external LNA. PIO[0], PIO[1] and the AUX_DAC can be used for this, as described in Table 11.1.
11.2
The BlueCore4-ROM CSP RF local oscillator and internal digital clocks are derived from the reference clock at
the BlueCore4-ROM CSP XTAL_IN input. This reference can be either an external clock or from a crystal
connected between XTAL_IN and XTAL_OUT. The crystal connection is described in Section 11.3.
11.2.1 External Mode
BlueCore4-ROM CSP can be configured to accept an external reference clock (from another device, such as
TCXO) at XTAL_IN by connecting XTAL_OUT to ground. This will cause XTAL_OUT to shut off, and it will not
drive to ground. The external clock can either be a digital level square wave or sinusoidal and this can be directly
coupled to XTAL_IN without the need for additional components. If the peaks of the reference clock are below
VSS_ANA or above VDD_ANA, it must be driven through a DC blocking capacitor (~33pF) connected to
XTAL_IN. A digital level reference clock gives superior noise immunity as the high slew rate clock edges have
lower voltage to phase conversion.
The external clock signal should meet the specifications in Table 11.2.
Notes:
BC41B143A-ds-002Pd
Frequency
Duty cycle
Edge Jitter (At Zero Crossing)
Signal Level
PSKEY_TXRX_PIO_CONTROL
(1)
(2)
(3)
The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies
VDD_ANA is 1.8V nominal
If the external clock is driven through a DC blocking capacitor then maximum allowable amplitude is
reduced from VDD_ANA to 800mV pk-pk
External Reference Clock Input (XTAL_IN)
(1)
Value
0
1
2
3
4
Table 11.1: PSKEY_TXRX_PIO_CONTROL Values
This material is subject to CSR’s non-disclosure agreement
Table 11.2: External Clock Specifications
Effect
PIO[0], PIO[1] and AUX_DAC are not used to control RF. Power ramping is
internal.
PIO[0] is high during RX and PIO[1] is high during TX. AUX_DAC is not
used. Power ramping is internal.
PIO[0] is high during RX and PIO[1] is high during TX. AUX_DAC is used to
set gain of external PA. Power ramping is external.
PIO[0] is low during RX and PIO[1] is low during TX. AUX_DAC is used to
set gain of external PA. Power ramping is external.
PIO[0] is high during RX and PIO[1] is high during TX. AUX_DAC is used to
set gain of external PA. Power ramping is internal.
© Cambridge Silicon Radio Limited 2005
Production Information
400mV pk-pk
7.5MHz
20:80
Min
-
16MHz
50:50
Typ
-
-
Device Terminal Descriptions
VDD_ANA
15ps rms
40MHz
80:20
Page 51 of 89
Max
(2)(3)