BC41B143A-ANN-E4 ETC, BC41B143A-ANN-E4 Datasheet - Page 75

• Manufacturer Part Number: BC41B143A-ANN-E4
• Description: Bluecore 4-rom CSP EDR Single Chip Bluetooth v2.0 + EDR System
• Manufacturer: ETC

11.7.10 PCM_CLK and PCM_SYNC Generation
BlueCore4-ROM CSP has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is
generating these signals by Direct Digital Synthesis (DDS) from BlueCore4-ROM CSP internal 4MHz clock.
Using this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz. The second is generating
PCM_CLK and PCM_SYNC by DDS from an internal 48MHz clock which allows a greater range of frequencies to
be generated with low jitter but consumes more power. This second method is selected by setting bit
48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the length
of PCM_SYNC can be either 8 or 16 cycles of PCM_CLK, determined by the LONG_LENGTH_SYNC_EN bit in
PSKEY_PCM_CONFIG32.
Equation 11.10 describes PCM_CLK frequency when being generated using the internal 48MHz clock:
The frequency of PCM_SYNC relative to PCM_CLK can be set using following equation:
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an
example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set
PSKEY_PCM_LOW_JITTER_CONFIG to
BC41B143A-ds-002Pd
PCM_SYNC
PCM_OUT
PCM_CLK
Equation 11.10: PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock
PCM_IN
t
susclksynch
Equation 11.11: PCM_SYNC Frequency Relative to PCM_CLK
Figure 11.27: PCM Slave Timing Short Frame Sync
This material is subject to CSR’s non-disclosure agreement
t
hsclksynch
© Cambridge Silicon Radio Limited 2005
t
supinsclkl
t
0x08080177
sclkh
t
f
dsclkhpout
MSB (LSB)
MSB (LSB)
=
f
f
=
sclk
CNT
CNT
Production Information
SYNC
t
hpinsclkl
t
tsclkl
PCM
_
_
RATE
LIMIT
_
.
_
LIMIT
CLK
×
24
×
MHz
8
LSB (MSB)
t
r
LSB (MSB)
,t
f
Device Terminal Descriptions
t
dpoutz
Page 75 of 89
t
dpoutz