BC41B143A-ANN-E4 ETC, BC41B143A-ANN-E4 Datasheet - Page 62

• Manufacturer Part Number: BC41B143A-ANN-E4
• Description: Bluecore 4-rom CSP EDR Single Chip Bluetooth v2.0 + EDR System
• Manufacturer: ETC

11.4.1 UART Bypass
11.4.2 UART Configuration while RESETB is Active
The UART interface for BlueCore4-ROM CSP while the IC is being held in reset is tri-stated. This allows the user
to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected
to this bus must tri-state when BlueCore4-ROM CSP RESETB pin is de-asserted and the firmware begins to run.
11.4.3 UART Bypass Mode
Alternatively, for devices that do not tri-state the UART bus, the UART bypass mode on BlueCore4-ROM CSP
can be used. The default state of BlueCore4-ROM CSP after reset is de-asserted is for the host UART bus to be
connected to the BlueCore4-ROM CSP UART, thereby allowing communication to BlueCore4-ROM CSP via the
UART. All UART bypass mode connections are implemented using CMOS technology and have signalling levels
of 0V and VDD_PADS
To apply the UART bypass mode, a BCCMD command is issued to BlueCore4-ROM CSP. At this command it
will switch the bypass to PIO[7:4] as shown in Figure 11.11. When the bypass mode has been invoked,
BlueCore4-ROM CSP enters the deep sleep state indefinitely.
To re-establish communication with BlueCore4-ROM CSP, the IC must be reset so that the default configuration
takes affect.
It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode
is invoked. Therefore it is not possible to have active Bluetooth links while operating the bypass mode.
The current consumption for a device in UART Bypass Mode is equal to the values quoted for a device in
standby mode.
Note:
BC41B143A-ds-002Pd
(1)
The range of the signalling level for the standard UART described in section 11.4 and the UART bypass
may differ between CSR BlueCore devices, as the power supply configurations are chip dependent. For
BlueCore4-ROM CSP the standard UART is supplied by VDD_USB so has signalling levels of 0V and
VDD_USB, whereas in the UART bypass mode the signals appear on the PIO[4:7] which are supplied
by VDD_PADS. Therefore the signalling levels are 0V and VDD_PADS.
Host Processor
RXD
CTS
RTS
TXD
(1)
.
Test Interface
This material is subject to CSR’s non-disclosure agreement
Figure 11.11: UART Bypass Architecture
© Cambridge Silicon Radio Limited 2005
UART_TX
UART_RTS
UART_CTS
UART_RX
RESETB
BlueCore4-ROM CSP
Production Information
UART
PIO[4]
PIO[5]
PIO[6]
PIO[7]
Device Terminal Descriptions
Another Device
TX
RTS
CTS
RX
Page 62 of 89