BC41B143A-ANN-E4 ETC, BC41B143A-ANN-E4 Datasheet - Page 52
BC41B143A-ANN-E4
Manufacturer Part Number
BC41B143A-ANN-E4
Description
Bluecore 4-rom CSP EDR Single Chip Bluetooth v2.0 + EDR System
Manufacturer
ETC
Datasheet
1.BC41B143A-ANN-E4.pdf
(89 pages)
- Current page: 52 of 89
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Device Terminal Descriptions
11.2.2 XTAL_IN Impedance in External Mode
The impedance of the XTAL_IN will not change significantly between operating modes, typically only 10fF. When
transitioning from deep sleep to an active state a spike of up to 1pC may be measured. For this reason it is
recommended that a buffered clock input is used to prevent other devices that share the clock signal from being
disrupted.
11.2.3 Clock Timing Accuracy
As Figure 11.3 shows, the 250ppm timing accuracy on the external clock is required 7ms after the assertion of
the system clock request line. This is to guarantee that the firmware can maintain timing accuracy in accordance
with the Bluetooth v2.0 + EDR Specification. Radio activity may occur after 11ms. Therefore, at this point the
timing accuracy of the external clock source must be within 20ppm. The CLK_REQ signal can be output from a
GPIO under the control of PSKEY_CLOCK_REQUEST_ENABLE.
Figure 11.3: TCXO Clock Accuracy
11.2.4 Clock Start-Up Delay
BlueCore4-ROM CSP hardware incorporates an automatic 5ms delay after the assertion of the system clock
request signal before running firmware. This is suitable for most applications using an external clock source.
However, there may be scenarios where the clock cannot be guaranteed to either exist or be stable after this
period. Under these conditions, BlueCore4-ROM CSP firmware provides a software function that extends the
system clock request signal by a period stored in PSKEY_CLOCK_STARTUP_DELAY. This value is set in units
of milliseconds from 5-31ms.
This PS Key allows the designer to optimise a system where clock latencies may be longer than 5ms while still
keeping the current consumption of BlueCore4-ROM CSP as low as possible. BlueCore4-ROM CSP consumes
about 2mA of current for the duration of PSKEY_CLOCK_STARTUP_DELAY before activating the firmware.
This material is subject to CSR’s non-disclosure agreement
BC41B143A-ds-002Pd
Page 52 of 89
Production Information
© Cambridge Silicon Radio Limited 2005
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