IDT72V263L7-5BC IDT, Integrated Device Technology Inc, IDT72V263L7-5BC Datasheet - Page 13

• Manufacturer Part Number: IDT72V263L7-5BC
• Description: IC FIFO 8192X18 7-5NS 100BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L7-5BC

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 133MHz
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L7-5BC

(32,769-m) writes for the IDT72V273, (65,537-m) writes for the IDT72V283
and (131,073-m) writes for the IDT72V293. The offset m is the full offset value.
The default setting for these values are stated in the footnote of Table 2.
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 513
writes for the IDT72V223, 1,025 writes for the IDT72V233, 2,049 writes for the
IDT72V243, 4,097 writes for the IDT72V253, 8,193 writes for the IDT72V263,
16,385 writes for the IDT72V273, 32,769 writes for the IDT72V283 and 65,537
writes for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected,
D = 1,025 writes for the IDT72V223, 2,049 writes for the IDT72V233, 4,097
writes for the IDT72V243, 8,193 writes for the IDT72V253, 16,385 writes for
the IDT72V263, 32,769 writes for the IDT72V273, 65,537 writes for the
IDT72V283 and 131,073 writes for the IDT72V293, respectively. Note that the
additional word in FWFT mode is due to the capacity of the memory plus output
register.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the PAE will go LOW when there are n+1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is empty.
buffered, and the IR flag output is double register-buffered.
12.
PROGRAMMING FLAG OFFSETS
72V233/72V243/72V253/72V263/72V273/72V283/72V293 has internal reg-
isters for these offsets. There are eight default offset values selectable during
Master Reset. These offset values are shown in Table 2. Offset values can also
TABLE 2 ⎯ DEFAULT PROGRAMMABLE FLAG OFFSETS
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1.
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
When configured in FWFT mode, the OR flag output is triple register-
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10 and
Full and Empty Flag offset values are user programmable. The IDT72V223/
LD
H
H
H
H
H
L
L
L
L
L
FSEL0 FSEL1
H
H
H
H
X
X
L
L
L
L
H
H
H
H
X
X
L
L
L
L
Offsets n,m
Serial Programming Mode
Parallel Programming Mode
IDT72V223
IDT72V233
All Modes
255
127
511
63
15
31
7
3
All Other
Modes
255
127
511
63
15
31
7
3
Offsets n,m
IDT72V243
(3)
(4)
x9 to x9
Mode
1,023
255
127
511
63
31
15
7
TM
13
NARROW BUS FIFO
be programmed into the FIFO in one of two ways; serial or parallel loading
method. The selection of the loading method is done using the LD (Load) pin.
During Master Reset, the state of the LD input determines whether serial or
parallel flag offset programming is enabled. A HIGH on LD during Master Reset
selects serial loading of offset values. A LOW on LD during Master Reset selects
parallel loading of offset values.
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
Master Reset, regardless of whether serial or parallel programming has been
selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
72V293 can be configured during the Master Reset cycle with either synchro-
nous or asynchronous timing for PAF and PAE flags by use of the PFM pin.
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 18 for synchronous
PAF timing and Figure 19 for synchronous PAE timing.
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure
20 for asynchronous PAF timing and Figure 21 for asynchronous PAE timing.
Offsets n,m
IDT72V253
IDT72V263
IDT72V273
All Modes
TM
In addition to loading offset values into the FIFO, it is also possible to read
Figure 3, Programmable Flag Offset Programming Sequence, summaries
The offset registers may be programmed (and reprogrammed) any time after
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
1,023
NARROW BUS FIFO
127
511
255
63
31
15
7
All Other
Modes
1,023
511
255
127
63
31
15
7
IDT72V283
Offsets n,m
x9 to x9
16,383
Mode
8,191
4,095
2,047
1,023
255
127
511
COMMERCIAL AND INDUSTRIAL
Offsets n,m
IDT72V293
All Modes
16,383
8,191
4,095
2,047
1,023
TEMPERATURE RANGES
511
255
127
FEBRUARY 11, 2009