IDT72V263L7-5BC IDT, Integrated Device Technology Inc, IDT72V263L7-5BC Datasheet - Page 19

• Manufacturer Part Number: IDT72V263L7-5BC
• Description: IC FIFO 8192X18 7-5NS 100BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L7-5BC

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 133MHz
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L7-5BC

SIGNAL DESCRIPTION
INPUTS:
DATA IN (D
(D
CONTROLS:
MASTER RESET (MRS)
state. This operation sets the internal read and write pointers to the first location
of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH.
with EF and FF are selected. EF will go LOW and FF will go HIGH. If FWFT/
SI is HIGH, then the First Word Fall Through mode (FWFT), along with IR and
OR, are selected. OR will go HIGH and IR will go LOW.
the Master Reset cycle.
Reset is required after power up, before a write operation can take place. MRS
is asynchronous.
PARTIAL RESET (PRS)
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH,
and HF goes HIGH.
or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall
Through mode is active, then OR will go HIGH, and IR will go LOW.
unchanged. The programming method (parallel or serial) currently active at
the time of Partial Reset is also retained. The output register is initialized to all
zeroes. PRS is asynchronous.
operation, when reprogramming programmable flag offset settings may not be
convenient.
ASYNCHRONOUS WRITE (ASYW)
mode of operation. If during Master Reset the ASYW input is LOW, then
Asynchronous operation of the write port will be selected. During Asynchro-
nous operation of the write port the WCLK input becomes WR input, this is the
Asynchronous write strobe input. A rising edge on WR will write data present
on the Dn inputs into the FIFO. (WEN must be tied LOW when using the write
port in Asynchronous mode).
(FF) operates in an asynchronous manner, that is, the full flag will be updated
based in both a write operation and read operation. Note, if Asynchronous
mode is selected, FWFT is not permissable. Refer to Figures 23, 24, 27 and
28 for relevant timing and operational waveforms.
ASYNCHRONOUS READ (ASYR)
mode of operation. If during a Master Reset the ASYR input is LOW, then
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
0
-D
Data inputs for 18-bit wide data (D
A Master Reset is accomplished whenever the MRS input is taken to a LOW
All control settings such as OW, IW, BE, RM, PFM and IP are defined during
During a Master Reset, the output register is initialized to all zeroes. A Master
See Figure 5, Master Reset Timing, for the relevant timing diagram.
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
Whichever mode is active at the time of Partial Reset, IDT Standard mode
Following Partial Reset, all values held in the offset registers remain
A Partial Reset is useful for resetting the device during the course of
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
The write port can be configured for either Synchronous or Asynchronous
When the write port is configured for Asynchronous operation the full flag
The read port can be configured for either Synchronous or Asynchronous
If FWFT/SI is LOW during Master Reset then the IDT Standard mode, along
8
).
0
- D
n
)
0
-D
17
) or data inputs for 9-bit wide data
TM
19
NARROW BUS FIFO
Asynchronous operation of the read port will be selected. During Asynchronous
operation of the read port the RCLK input becomes RD input, this is the
Asynchronous read strobe input. A rising edge on RD will read data from the
FIFO via the output register and Qn port. (REN must be tied LOW during
Asynchronous operation of the read port).
asynchronous manner.
must be operating on IDT standard mode, FWFT mode is not permissible if the
read port is Asynchronous. The Empty Flag (EF) operates in an Asynchronous
manner, that is, the empty flag will be updated based on both a read operation
and a write operation. Refer to figures 25, 26, 27 and 28 for relevant timing and
operational waveforms.
RETRANSMIT (RT)
accessed again. There are 2 modes of Retransmit operation, normal latency
and zero latency. There are two stages to Retransmit: first, a setup procedure
that resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting at the
beginning of the memory.
REN and WEN must be HIGH before bringing RT LOW. When zero latency
is utilized, REN does not need to be HIGH before bringing RT LOW.
Retransmit setup by setting EF LOW. The change in level will only be noticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
may begin starting with the first location in memory. Since IDT Standard mode
is selected, every word read including the first word following Retransmit setup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
setup by setting OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
contents of the first location appear on the outputs. Since FWFT mode is selected,
the first word appears on the outputs, no LOW on REN is necessary. Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing
diagram.
Retransmit Mode (RM) pin during a Master Reset. This can be applied to both
IDT Standard mode and FWFT mode.
RETRANSMIT LATENCY MODE (RM)
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero-
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
retransmitted will be placed on the output register with respect to the same RCLK
edge that initiated the retransmit based on RT being LOW.
Mode). Refer to Figure 14 for Retransmit Timing with zero latency (FWFT
Mode).
TM
A zero-latency retransmit timing mode can be selected using the Retransmit
If zero-latency retransmit operation is selected the first data word to be
Refer to Figure 13 for Retransmit Timing with zero latency (IDT Standard
The OE input provides three-state control of the Qn output bus, in an
When the read port is configured for Asynchronous operation the device
The Retransmit operation allows data that has already been read to be
Retransmit setup is initiated by holding RT LOW during a rising RCLK edge.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
When EF goes HIGH, Retransmit setup is complete and read operations
If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit
When OR goes LOW, Retransmit setup is complete; at the same time, the
In Retransmit operation, zero-latency mode can be selected using the
NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009