IDT72V263L7-5BC IDT, Integrated Device Technology Inc, IDT72V263L7-5BC Datasheet - Page 3

• Manufacturer Part Number: IDT72V263L7-5BC
• Description: IC FIFO 8192X18 7-5NS 100BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L7-5BC

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 133MHz
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L7-5BC

which can assume either an 18-bit or a 9-bit width as determined by the state
of external control pins Input Width (IW) and Output Width (OW) during the Master
Reset cycle.
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
WCLK when WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the WEN input should be tied to its active state, (LOW).
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
DESCRIPTION (CONTINUED)
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
PIN CONFIGURATIONS (CONTINUED)
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
Each FIFO has a data input port (D
The input port can be selected as either a Synchronous (clocked) interface,
The output port can be selected as either a Synchronous (clocked) interface,
A
B
C
D
H
K
E
F
G
J
ASYW
WCLK
WEN
D17
D13
D11
D16
D5
D8
D6
1
SEN
MRS
PRS
D14
D12
D15
IW
D9
D7
D4
2
n
) and a data output port (Q
A1 BALL PAD CORNER
FWFT/SI
FF/IR
V
V
V
V
D10
BGA: 1mm pitch, 11mm x 11mm (BC100-1, order code: BC)
LD
D2
D3
CC
CC
CC
CC
3
GND
GND
GND
GND
PAF
V
OW
V
D0
D1
4
CC
CC
n
), both of
FSEL0
TRST
GND
GND
GND
GND
TMS
V
V
HF
5
CC
CC
TM
TOP VIEW
3
NARROW BUS FIFO
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the REN input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, and the OE input used
to provide three-state control of the outputs, Qn.
to f
of the one clock input with respect to the other.
Standard mode and First Word Fall Through (FWFT) mode.
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
to the data output lines after three transitions of the RCLK signal. A REN does
FSEL1
GND
GND
GND
GND
TDI
V
TCK
V
BE
TM
MAX
The frequencies of both the RCLK and the WCLK signals may vary from 0
In IDT Standard mode, the first word written to an empty FIFO will not appear
In FWFT mode, the first word written to an empty FIFO is clocked directly
CC
There are two possible timing modes of operation with these devices: IDT
CC
6
NARROW BUS FIFO
with complete independence. There are no restrictions on the frequency
ASYR
GND
GND
GND
GND
TDO
V
V
Q0
IP
CC
CC
7
PFM
PAE
V
V
V
V
V
Q1
Q3
Q2
CC
CC
CC
CC
CC
8
EF/OR
Q16
Q14
Q13
Q11
RM
RT
Q5
Q9
Q4
9
COMMERCIAL AND INDUSTRIAL
4666 drw02b
RCLK
REN
Q17
Q15
Q12
Q10
OE
Q7
Q8
Q6
10
TEMPERATURE RANGES
FEBRUARY 11, 2009