IDT72V263L7-5BC IDT, Integrated Device Technology Inc, IDT72V263L7-5BC Datasheet - Page 22

• Manufacturer Part Number: IDT72V263L7-5BC
• Description: IC FIFO 8192X18 7-5NS 100BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L7-5BC

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 133MHz
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L7-5BC

IDT72V263, (32,768-m) writes for the IDT72V273, (65,536-m) writes for the
IDT72V283 and (131,072-m) writes for the IDT72V293. The offset “m” is the
full offset value. The default setting for this value is stated in Table 2.
will go LOW after (513-m) writes for the IDT72V223, (1,025-m) writes for the
IDT72V233, (2,049-m) writes for the IDT72V243, (4,097-m) writes for the
IDT72V253, (8,193-m) writes for the IDT72V263, (16,385-m) writes for the
IDT72V273, (32,769-m) writes for the IDT72V283 and (65,537-m) writes for
the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, the PAF
will go LOW after (1,025-m) writes for the IDT72V223, (2,049-m) writes for the
IDT72V233, (4,097-m) writes for the IDT72V243, (8,193-m) writes for the
IDT72V253, (16,385-m) writes for the IDT72V263, (32,769-m) writes for the
IDT72V273, (65,537-m) writes for the IDT72V283 and (131,073-m) writes for
the IDT72V293. The offset m is the full offset value. The default setting for this
value is stated in Table 2.
Standard and FWFT Mode), for the relevant timing information.
on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF
configuration is selected, the PAF is updated on the rising edge of WCLK. See
Figure 20 for Asynchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode).
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in Table 2.
in the FIFO. The default setting for this value is stated in Table 2.
(IDT Standard and FWFT Mode), for the relevant timing information.
on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
In FWFT mode, if x18 Input or x18 Output bus Width is selected, the PAF
See Figure 18, Synchronous Programmable Almost-Full Flag Timing (IDT
See Figure 19, Synchronous Programmable Almost-Empty Flag Timing
If asynchronous PAF configuration is selected, the PAF is asserted LOW
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
In FWFT mode, the PAE will go LOW when there are n+1 words or less
If asynchronous PAE configuration is selected, the PAE is asserted LOW
22
configuration is selected, the PAE is updated on the rising edge of RCLK. See
Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
HALF-FULL FLAG (HF)
beyond half-full sets HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
HF will go LOW after (D/2 + 1) writes to the FIFO. If x18 Input or x18 Output
bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233,
2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263,
16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the
IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024
for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192
for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273,
65,536 for the IDT72V283 and 131,072 for the IDT72V293.
will go LOW after (D-1/2 + 2) writes to the FIFO. If x18 Input or x18 Output bus
Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049
for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385
for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the
IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the
IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for
the IDT72V283 and 131,073 for the IDT72V293.
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
bit wide data.
TM
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
In IDT Standard mode, if no reads are performed after reset (MRS or PRS),
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Mode),
(Q
NARROW BUS FIFO
0
- Q
17
) data outputs for 18-bit wide data or (Q
0
-Q
n
)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009
0
- Q
8
) data outputs for 9-