IDT72V263L7-5BC IDT, Integrated Device Technology Inc, IDT72V263L7-5BC Datasheet - Page 7

• Manufacturer Part Number: IDT72V263L7-5BC
• Description: IC FIFO 8192X18 7-5NS 100BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L7-5BC

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 133MHz
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L7-5BC

NOTE:
1. Inputs should not change state after Master Reset.
PIN DESCRIPTION (BGA PACKAGE ONLY)
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 41-44 and Figures 31-33.
PIN DESCRIPTION-CONTINUED (TQFP & BGA PACKAGES)
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
ASYR
ASYW
TCK
TDI
TDO
TMS
TRST
RM
RT
SEN
WCLK/
WR
WEN
V
Symbol
Symbol
CC
(2)
(1)
(2)
(2)
(2)
(2)
(1)
(1)
Retransmit Timing
Mode
Retransmit
Serial Enable
Write Clock/
Write Strobe
Write Enable
+3.3V Supply
Asynchronous
Read Port
Asynchronous
Write Port
JTAG Clock
JTAG Test Data
Input
JTAG Test Data
Output
JTAG Mode Select
JTAG Reset
Name
Name
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
normal latency mode.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH
in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable
flag settings. RT is useful to reread data from the first physical location of the FIFO.
SEN enables serial loading of programmable flag offsets.
If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK
writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the
FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state). Asynchronous operation
of the WCLK/WR input is only available in the BGA package.
WEN enables WCLK for writing data into the FIFO memory and offset registers.
These are V
A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
will select Asynchronous operation.
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the
device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change
on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register.
An internal pull-up resistor forces TDI HIGH if left unconnected.
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass
Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through
its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically reset
upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP
controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG function is used
but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper FIFO operation. If the
JTAG function is not used then this signal needs to be tied to GND.
CC
supply inputs and must be connected to the 3.3V supply rail.
TM
7
NARROW BUS FIFO
TM
NARROW BUS FIFO
Description
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009