IDT72V263L7-5BC IDT, Integrated Device Technology Inc, IDT72V263L7-5BC Datasheet - Page 43

• Manufacturer Part Number: IDT72V263L7-5BC
• Description: IC FIFO 8192X18 7-5NS 100BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L7-5BC

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 133MHz
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L7-5BC

NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
1149.1) for the full state diagram
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the FIFO memory and must be reset after power up of the device. See
TRST description for more details on TAP controller reset.
CAPTURE-DR
Register.
SHIFT-DR
of TCLK in the TDI/TDO path and shifted out serially, LSB first at the falling edge
of TCLK towards the output.
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
All state transitions within the TAP controller occur at the rising edge of the
Data is loaded from the parallel input pins or core outputs into the Data
The previously captured data is shifted in serially, LSB first at the rising edge
Input = TMS
1
0
Test-Logic
Run-Test/
Reset
Idle
0
Figure 33. TAP Controller State Diagram
1
1
0
1
Update-DR
Capture-DR
Pause-DR
Exit2-DR
DR-Scan
Shift-DR
EXit1-DR
Select-
TM
0
0
43
0
1
1
1
NARROW BUS FIFO
0
UPDATE-DR
parallel outputs in this state to be accessed through the internal bus.
EXIT1-DR / EXIT2-DR
to TCK while in this state causes the controller to enter the Update-DR state. This
terminates the scanning process. All test data registers selected by the current
instruction retain their previous state unchanged.
PAUSE-DR
between TDI and TDO to be temporarily halted. All test data registers selected
by the current instruction retain their previous state unchanged.
similar to Data registers. These instructions operate on the instruction registers.
0
0
TM
The shifting process has been completed. The data is latched into their
This is a temporary controller state. If TMS is held high, a rising edge applied
This controller state allows shifting of the test data register in the serial path
Capture-IR, Shift-IR and Update-IR, Exit-IR and Pause-IR are
NARROW BUS FIFO
1
1
0
1
1
1
1
1
Capture-IR
Update-IR
Pause-IR
Exit2-IR
IR-Scan
Exit1-IR
Shift-IR
Select-
1
0
0
0
0
4666 drw36
0
0
COMMERCIAL AND INDUSTRIAL
1
TEMPERATURE RANGES
FEBRUARY 11, 2009