IDT72V263L7-5BC IDT, Integrated Device Technology Inc, IDT72V263L7-5BC Datasheet - Page 17

• Manufacturer Part Number: IDT72V263L7-5BC
• Description: IC FIFO 8192X18 7-5NS 100BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L7-5BC

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 133MHz
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L7-5BC

SERIAL PROGRAMMING MODE
programming of PAE and PAF values can be achieved by using a combination
of the LD, SEN, WCLK and SI input pins. Programming PAE and PAF proceeds
as follows: when LD and SEN are set LOW, data on the SI input are written,
one bit for each WCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. If x9 to x9 mode is selected, a total of 20 bits for the
IDT72V223, 22 bits for the IDT72V233, 24 bits for the IDT72V243, 26 bits for
the IDT72V253, 28 bits for the IDT72V263, 30 bits for the IDT72V273, 32 bits
for the IDT72V283 and 34 bits for the IDT72V293. For any other mode of
operation (that includes x18 bus width on either the Input or Output), minus 2
bits from the values above. So, a total of 18 bits for the IDT72V223, 20 bits for
the IDT72V233, 22 bits for the IDT72V243, 24 bits for the IDT72V253, 26 bits
for the IDT72V263, 28 bits for the IDT72V273, 30 bits for the IDT72V283 and
32 bits for the IDT72V293. See Figure 15, Serial Loading of Programmable
Flag Registers, for the timing diagram for this mode.
selectively. PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
programming sequence. In this case, the programming of all offset bits does not
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing LD and SEN HIGH, data can be written to FIFO memory via
D
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruption of serial programming is desired, it is sufficient either to set LD LOW
and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN
are both restored to a LOW level, serial offset programming continues.
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above criteria;
PAF will be valid after two more rising WCLK edges plus t
after the next two rising RCLK edges plus t
PARALLEL PROGRAMMING MODE
programming of PAE and PAF values can be achieved by using a combination
of the LD, WCLK , WEN and D
bus width and output bus width both set to x9, then the total number of write
operations required to program the offset registers is 4 for the IDT72V223/
72V233/72V243/72V253/72V263/72V273/72V283 or 6 for the IDT72V293.
Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a
detailed diagram of the data input lines D
ming. If the FIFO is configured for an input to output bus width of x9 to x18, x18
to x9 or x18 to x18, then the following number of write operations are required.
For an input bus width of x18 a total of 2 write operations will be required to
program the offset registers for the IDT72V223/72V233/72V243/72V253/
72V263/72V273/72V283/72V293. For an input bus width of x9 a total of 4 write
operations will be required to program the offset registers for the IDT72V223/
72V233/72V243/72V253/72V263/72V273/72V283/72V293. Refer to Figure
3, Programmable Flag Offset Programming Sequence, for a detailed diagram.
for x18 bus width proceeds as follows: when LD and WEN are set LOW, data
on the inputs Dn are written into the LSB of the Empty Offset Register on the first
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
n
by toggling WEN. When WEN is brought HIGH with LD and SEN restored
If Serial Programming mode has been selected, as described above, then
Using the serial method, individual registers cannot be programmed
Write operations to the FIFO are allowed before and during the serial
From the time serial programming has begun, neither programmable flag
It is not possible to read the flag offset values in a serial mode.
If Parallel Programming mode has been selected, as described above, then
For example, programming PAE and PAF on the IDT72V293 configured
n
input pins. If the FIFO is configured for an input
0
-Dn used during parallel program-
PAE
plus t
SKEW2
PAF
, PAE will be valid
.
TM
17
NARROW BUS FIFO
LOW-to-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition
of WCLK, data are written into the MSB of the Empty Offset Register. On the third
LOW-to-HIGH transition of WCLK, data are written into the LSB of the Full Offset
Register. On the fourth LOW-to-HIGH transition of WCLK, data are written into
the MSB of the Full Offset Register. The fifth LOW-to-HIGH transition of WCLK,
data are written, once again to the Empty Offset Register. Note that for x9 bus
width, one extra Write cycle is required for both the Empty Offset Register and
Full Offset Register. See Figure 16, Parallel Loading of Programmable Flag
Registers, for the timing diagram for this mode.
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A Master Reset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers. Refer to Figure 3, Programmable
Flag Offset Programming Sequence, for a detailed diagram of the data input
lines D
programming sequence. In this case, the programming of all offset registers
does not have to occur at one time. One, two or more offset registers can be
written and then by bringing LD HIGH, write operations can be redirected to
the FIFO memory. When LD is set LOW again, and WEN is LOW, the next offset
register in sequence is written to. As an alternative to holding WEN LOW and
toggling LD, parallel programming can also be interrupted by setting LD LOW
and toggling WEN.
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria; PAF will be valid after
two more rising WCLK edges plus t
RCLK edges plus t
register pointer. The contents of the offset registers can be read on the Q
pins when LD is set LOW and REN is set LOW. If the FIFO is configured for an
input bus width and output bus width both set to x9, then the total number of read
operations required to read the offset registers is 4 for the IDT72V223/72V233/
72V243/72V253/72V263/72V273/72V283 or 6 for the IDT72V293. Refer to
Figure 3, Programmable Flag Offset Programming Sequence, for a detailed
diagram of the data input lines D
FIFO is configured for an input to output bus width of x9 to x18, x18 to x9 or
x18 to x18, then the following number of read operations are required: for an
output bus width of x18 a total of 2 read operations will be required to read the
offset registers for the IDT72V223/72V233/72V243/72V253/72V263/72V273/
72V283/72V293. For an output bus width of x9 a total of 4 read operations will
be required to read the offset registers for the IDT72V223/72V233/72V243/
72V253/72V263/72V273/72V283/72V293. Refer to Figure 3, Program-
mable Flag Offset Programming Sequence, for a detailed diagram. For
example, reading PAE and PAF on the IDT72V293 configured for x18 bus
width proceeds as follows: data are read via Q
on the first and second LOW-to-HIGH transition of RCLK. Upon the third and
fourth LOW-to-HIGH transition of RCLK, data are read from the Full Offset
Register. The fifth and sixth transition of RCLK reads, once again, from the
Empty Offset Register. Note that for a x9 bus width, one extra Read cycle is
required for both the Empty Offset Register and Full Offset Register. See Figure
17, Parallel Read of Programmable Flag Registers, for the timing diagram for
this mode.
TM
The act of writing offsets in parallel employs a dedicated write offset register
Write operations to the FIFO are allowed before and during the parallel
Note that the status of a programmable flag (PAE or PAF) output is invalid
The act of reading the offset registers employs a dedicated read offset
NARROW BUS FIFO
0
-Dn used during parallel programming.
PAE
plus t
SKEW2
0
-Dn used during parallel programming. If the
PAF
.
, PAE will be valid after the next two rising
COMMERCIAL AND INDUSTRIAL
n
from the Empty Offset Register
TEMPERATURE RANGES
FEBRUARY 11, 2009
0
-Q
n