IDT72V263L7-5BC IDT, Integrated Device Technology Inc, IDT72V263L7-5BC Datasheet - Page 44

• Manufacturer Part Number: IDT72V263L7-5BC
• Description: IC FIFO 8192X18 7-5NS 100BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L7-5BC

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 133MHz
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L7-5BC

THE INSTRUCTION REGISTER
processor at the rising edge of TCLK.
register to be accessed, or both. The instruction shifted into the register is latched
at the completion of the shifting process when the TAP controller is at Update-
IR state.
which can hold instruction data. These mandatory cells are located nearest the
serial outputs they are the least significant bits.
TEST DATA REGISTER
Boundary Scan register and Device ID register.
and a common serial data output.
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
TEST BYPASS REGISTER
to TDO. It contains a single stage shift register for a minimum length in serial path.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
operation of the device in response to the BYPASS instruction.
THE BOUNDARY-SCAN REGISTER
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
THE DEVICE IDENTIFICATION REGISTER
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
is dropped in the 11-bit Manufacturer ID field.
72V293, the Part Number field contains the following values:
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
The Instruction register allows an instruction to be shifted in serially into the
The Instruction is used to select the test to be performed, or the test data
The instruction register must contain 4 bit instruction register-based cells
The Test Data register contains three test data registers: the Bypass, the
These registers are connected in parallel between a common serial input
The following sections provide a brief description of each element. For a
The register is used to allow test data to flow through the device from TDI
The operation of the bypass register should not have any effect on the
The Boundary Scan Register allows serial data TDI be loaded in to or read
The Device Identification Register is a Read Only 32-bit register used to
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
For the IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
IDT72V223
IDT72V233
IDT72V243
IDT72V253
IDT72V263
IDT72V273
IDT72V283
IDT72V293
Device
Part# Field
04ED
04EC
04EF
04EE
04EB
04EA
04E9
04E8
44
IDT72V223/233/243/253/263/273/283/293 JTAG Device Identification Register
JTAG INSTRUCTION REGISTER
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
16 different possible instructions. Instructions are decoded as follows.
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
EXTEST
board level interconnection check.
IDCODE
out manufacture’s identity, part number and version number.
SAMPLE/PRELOAD
loaded onto the latched parallel outputs of the boundary-scan shift register prior
to selection of the boundary-scan test instruction. The SAMPLE instruction
allows a snapshot of data flowing from the system pins to the on-chip logic or vice
versa.
HIGH-Z
state.
BYPASS
provide a minimum-length serial path between the TDI and the TDO pins of the
device when no test operation of the device is required.
31(MSB)
Version (4 bits)
0X0
Hex
Value
0x00
0x02
0x01
0x03
0x0F
TM
The Instruction register allows instruction to be serially input into the device
•
•
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
The following sections provide a brief description of each instruction. For
The mandatory EXTEST instruction is provided for external circuity and
This instruction is provided to select Device Identification Register to read
The mandatory SAMPLE/PRELOAD instruction allows data values to be
This instruction places all the output pins on the device into a high impedance
The Bypass instruction contains a single shift-register stage and is set to
NARROW BUS FIFO
Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
Instruction
EXTEST
IDCODE
SAMPLE/PRELOAD
HI-Z
BYPASS
Table 6. JTAG Instruction Register Decoding
28 27
Part Number (16-bit) Manufacturer ID (11-bit)
Function
Select Boundary Scan Register
Select Chip Identification data register
Select Boundary Scan Register
JTAG
Select Bypass Register
COMMERCIAL AND INDUSTRIAL
12 11
0X33
TEMPERATURE RANGES
FEBRUARY 11, 2009
1 0(LSB)
1