IDT72V263L7-5BC IDT, Integrated Device Technology Inc, IDT72V263L7-5BC Datasheet - Page 40

• Manufacturer Part Number: IDT72V263L7-5BC
• Description: IC FIFO 8192X18 7-5NS 100BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L7-5BC

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 133MHz
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L7-5BC

For the x18 Input or x18 Output bus Width: 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18 and 131,072 x 18
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
greater than 512 when the x18 Input or x18 Output bus Width is selected, 1,024
for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192
for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and
65,536 for the IDT72V293. When both x9 Input and x9 Output bus Widths are
selected, depths greater than 1,024 can be adapted for the IDT72V223, 2,048
for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384
for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and
131,072 for the IDT72V293. In FWFT mode, the FIFOs can be connected in
series (the data outputs of one FIFO connected to the data inputs of the next)
with no external logic necessary. The resulting configuration provides a total
depth equivalent to the sum of the depths associated with each single FIFO.
Figure 30 shows a depth expansion using two IDT72V223/72V233/72V243/
72V253/72V263/72V273/72V283/72V293 devices.
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain–no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the data
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
where N is the number of FIFOs in the expansion and T
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
For both x9 Input and x9 Output bus Widths: 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9, 131,072 x 9 and 262,144 x 9
The IDT72V223 can easily be adapted to applications requiring depths
Care should be taken to select FWFT mode during Master Reset for all FIFOs
For an empty expansion configuration, the amount of time it takes for OR of
DATA IN
FWFT/SI
WRITE CLOCK
WRITE ENABLE
INPUT READY
n
(N – 1)*(4*transfer clock) + 3*T
WEN
WCLK
IR
Dn
FWFT/SI
72V223
72V233
72V243
72V253
72V263
72V273
72V283
72V293
IDT
TRANSFER CLOCK
Figure 30. Block Diagram of Depth Expansion
RCLK
RCLK
RCLK
REN
OE
OR
Qn
is the RCLK period.
GND
n
40
Note that extra cycles should be added for the possibility that the t
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
configuration will "bubble up" from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
created in one FIFO of the chain, that FIFO's IR line goes LOW, enabling the
preceding FIFO to write a word to fill it.
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the t
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
TM
The "ripple down" delay is only noticeable for the first word written to an empty
The first free location created by reading from a full depth expansion
For a full expansion configuration, the amount of time it takes for IR of the first
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
NARROW BUS FIFO
IR
WCLK
WEN
Dn
(N – 1)*(3*transfer clock) + 2 T
FWFT/SI
72V223
72V233
72V243
72V253
72V263
72V273
72V283
72V293
IDT
COMMERCIAL AND INDUSTRIAL
RCLK
REN
OR
OE
Qn
TEMPERATURE RANGES
OUTPUT READY
OUTPUT ENABLE
n
FEBRUARY 11, 2009
READ ENABLE
READ CLOCK
WCLK
WCLK
DATA OUT
4666 drw33
is the WCLK
SKEW1
SKEW1