IDT72V263L7-5BC IDT, Integrated Device Technology Inc, IDT72V263L7-5BC Datasheet - Page 18

• Manufacturer Part Number: IDT72V263L7-5BC
• Description: IC FIFO 8192X18 7-5NS 100BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L7-5BC

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 133MHz
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L7-5BC

writes to the FIFO. The interruption is accomplished by deasserting REN, LD,
or both together. When REN and LD are restored to a LOW level, reading of
the offset registers continues where it left off. It should be noted, and care should
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT OPERATION
accessed again. There are 2 modes of Retransmit operation, normal latency
and zero latency. There are two stages to Retransmit: first, a setup procedure
that resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting at the
beginning of memory.
REN and WEN must be HIGH before bringing RT LOW. When zero latency is
utilized, REN does not need to be HIGH before bringing RT LOW. At least two
words, but no more than D - 2 words should have been written into the FIFO,
and read from the FIFO, between Reset (Master or Partial) and the time of
Retransmit setup. If x18 Input or x18 Output bus Width is selected, D = 512 for
the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for
the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768
for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output
bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the
IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for
the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and
131,072 for the IDT72V293. In FWFT mode, if x18 Input or x18 Output bus Width
is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for
the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385
for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the
IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
It is permissible to interrupt the offset register read sequence with reads or
The Retransmit operation allows data that has already been read to be
Retransmit setup is initiated by holding RT LOW during a rising RCLK edge.
Parallel reading of the offset registers is always permitted regardless of
18
IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for
the IDT72V283 and 131,073 for the IDT72V293.
Retransmit setup by setting EF LOW. The change in level will only be noticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
may begin starting with the first location in memory. Since IDT Standard mode
is selected, every word read including the first word following Retransmit setup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
setup by setting OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
contents of the first location appear on the outputs. Since FWFT mode is selected,
the first word appears on the outputs, no LOW on REN is necessary. Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing
diagram.
PAF flags begin with the rising edge of RCLK that the RT is setup on. PAE is
synchronized to RCLK, thus on the second rising edge of RCLK after RT is setup,
the PAE flag will be updated. HF is asynchronous, thus the rising edge of RCLK
that RT is setup will update HF. PAF is synchronized to WCLK, thus the second
rising edge of WCLK that occurs t
is setup will update PAF. RT is synchronized to RCLK.
latency" or "zero latency". Figure 11 and Figure 12 mentioned previously,
relate to "normal latency". Figure 13 and Figure 14 show "zero latency"
retransmit operation. Zero latency basically means that the first data word to be
retransmitted, is placed onto the output register with respect to the RCLK pulse
that initiated the retransmit.
TM
For either IDT Standard mode or FWFT mode, updating of the PAE, HF and
The Retransmit function has the option of 2 modes of operation, either "normal
If IDT Standard mode is selected, the FIFO will mark the beginning of the
When EF goes HIGH, Retransmit setup is complete and read operations
If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit
When OR goes LOW, Retransmit setup is complete; at the same time, the
NARROW BUS FIFO
SKEW
after the rising edge of RCLK that RT
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009