IDT72V263L7-5BC IDT, Integrated Device Technology Inc, IDT72V263L7-5BC Datasheet - Page 33

• Manufacturer Part Number: IDT72V263L7-5BC
• Description: IC FIFO 8192X18 7-5NS 100BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L7-5BC

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 133MHz
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L7-5BC

NOTE:
1. This diagram is based on programming the IDT72V293 x18 bus width. Add one extra cycle to both the PAE offset and PAF offset for x9 bus width.
NOTES:
1. OE = LOW.
2. This diagram is based on programming the IDT72V293 x18 bus width. Add one extra cycle to both the PAE offset and PAF offset for x9 bus width.
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
D
Q
WCLK
RCLK
WEN
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253,
8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024
for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283
and 131,072 for the IDT72V293.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193
for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the
IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073
for the IDT72V293.
rising edge of RCLK and the rising edge of WCLK is less than t
0
REN
WCLK
0
PAF
SKEW2
RCLK
- D
WEN
- Q
REN
LD
16
LD
16
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
DATA IN OUTPUT
t
CLKH
REGISTER
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
t
ENS
LDS
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENS
t
CLKL
t
CLKH
D-(m+1) words in FIFO
PAE OFFSET (LSB)
t
t
CLK
ENH
t
CLKH
t
t
A
t
LDH
t
t
ENS
t
ENH
LDS
t
CLKL
DS
t
CLK
1
t
( 2)
CLKL
PAE OFFSET
SKEW2
(LSB)
t
t
t
ENH
LDH
DH
PAE OFFSET (MSB)
, then the PAF deassertion time may be delayed one extra WCLK cycle.
t
A
2
TM
t
DS
t
PAFS
33
NARROW BUS FIFO
TM
PAE OFFSET
NARROW BUS FIFO
t
ENS
(MSB)
t
SKEW2
t
PAF OFFSET (LSB)
DH
(3)
t
A
t
t
DS
D - m words in FIFO
ENH
1
PAF OFFSET
(LSB)
PAF OFFSET (MSB)
t
COMMERCIAL AND INDUSTRIAL
DH
(2)
t
A
t
t
LDH
ENH
2
TEMPERATURE RANGES
t
PAFS
t
DS
PAFS
FEBRUARY 11, 2009
). If the time between the
PAF OFFSET
(MSB)
D-(m+1) words
in FIFO
4666 drw19
4666 drw21
4666 drw20
t
t
t
ENH
DH
LDH
( 2)