IDT72V263L7-5BC IDT, Integrated Device Technology Inc, IDT72V263L7-5BC Datasheet - Page 2

• Manufacturer Part Number: IDT72V263L7-5BC
• Description: IC FIFO 8192X18 7-5NS 100BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L7-5BC

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 133MHz
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L7-5BC

DESCRIPTION:
72V293 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO)
memories with clocked read and write controls and a flexible Bus-Matching x9/
x18 data flow. These FIFOs offer numerous improvements over previous
SuperSync FIFOs, including the following:
• Flexible x9/x18 Bus-Matching on both read and write ports
• The limitation of the frequency of one clock input with respect to the other
PIN CONFIGURATIONS
NOTE:
1. DNC = Do Not Connect.
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs,
RCLK or WCLK, is running at the higher frequency.
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
INDEX
DNC
DNC
WEN
SEN
GND
GND
D17
V
V
D16
D15
D14
D13
D12
D11
D10
V
D9
D8
IW
CC
CC
CC
(1)
(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TQFP (PN80-1, order code: PF)
TOP VIEW
2
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written to an
• Asynchronous/Synchronous translation on the read or write ports
• High density offerings up to 1 Mbit
video, telecommunications, data communications and other applications that
need to buffer large amounts of data and match busses of unequal sizes.
TM
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)
Bus-Matching SuperSync FIFOs are particularly appropriate for network,
NARROW BUS FIFO
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
COMMERCIAL AND INDUSTRIAL
4666 drw02
TEMPERATURE RANGES
V
RT
OE
V
Q17
Q16
GND
GND
Q15
Q14
Q13
Q12
GND
Q11
GND
Q9
Q8
Q7
Q10
V
CC
CC
CC
FEBRUARY 11, 2009