S25FL004K Meet Spansion Inc., S25FL004K Datasheet - Page 16

• Manufacturer Part Number: S25FL004K
• Description: 4-mbit / 8-mbit / 16-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

6.1
16
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
Status Register
BUSY
Write Enable Latch (WEL)
Block Protect Bits (BP2, BP1, BP0)
Top/Bottom Block Protect (TB)
Sector/Block Protect (SEC)
Complement Protect (CMP)
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page
Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/
Program Security Register instruction. During this time the device will ignore further instructions except for the
Read Status Register and Erase/Program Suspend instruction (see t
AC Electrical Characteristics on page
instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further
instructions.
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write
Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state
occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page
Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and
Program Security Register.
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2)
that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register
Instruction (see t
can be protected from Program and Erase instructions (see
for the Block Protection Bits is 0 (none of the array is protected.)
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top
(TB=0) or the Bottom (TB=1) of the array as shown in
The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending
on the state of the SRP0, SRP1 and WEL bits.
The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect
either 4-kB Sectors (SEC=1) or 64-kB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as
shown in
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in
conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once
CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance,
when CMP=0, a top 4-kB sector can be protected while the rest of the array is not; when CMP=1, the top 4-kB
sector will become unprotected while the rest of the array become read-only. Please refer to
details. The default setting is CMP=0.
Table
6.1. The default setting is SEC=0.
W
in AC Electrical Characteristics
S25FL004K / S25FL008K / S25FL016K
64). When the program, erase or write status/security register
D a t a
on page
Table 6.1, Status Register Protection Bits on page
S h e e t
Table 6.3 on page
64). All, none or a portion of the memory array
W
, t
S25FL004K-016K_00_02 July 14, 2011
PP
, t
SE
20). The factory default setting
, t
BE
, and t
CE
in
Table 6.1
Section 8.6,
for
17.