S25FL004K Meet Spansion Inc., S25FL004K Datasheet - Page 17

• Manufacturer Part Number: S25FL004K
• Description: 4-mbit / 8-mbit / 16-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

July 14, 2011 S25FL004K-016K_00_02
6.1.7
6.1.8
6.1.9
6.1.10
Status Register Protect (SRP1, SRP0)
Erase/Program Suspend Status (SUS)
Security Register Lock Bits (LB3, LB2, LB1)
Quad Enable (QE)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8
and S7). The SRP bits control the method of write protection: software protection, hardware protection, power
supply lock-down or one time programmable (OTP) protection.
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available upon special order. Please contact Spansion for details.
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/
Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah)
instruction as well as a power-down, power-up cycle.
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The
default state of LB[3:1] is 0, Security Registers are unlocked. LB[3:1] can be set to 1 individually using the
Write Status Register instruction. LB[3:1] are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-byte Security Register will become read-only permanently.
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
operation. When the QE bit is set to a 0 state (factory default), the WP# pin and HOLD# are enabled. When
the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and WP# and HOLD# functions are disabled.
Note: If the WP# or HOLD# pins are tied directly to the power supply or ground during standard SPI or Dual
SPI operation, the QE bit should never be set to a 1.
SRP1
0
0
0
1
1
SRP0
0
1
1
0
1
WP#
X
X
X
0
1
D a t a
S25FL004K / S25FL008K / S25FL016K
Software Protection
Hardware Protected
Hardware Unprotected
Power Supply Lock-
Down
One Time Program
Status Register
Table 6.1 Status Register Protection Bits
S h e e t
(2)
WP# pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
When WP# pin is low the Status Register locked and can not be
written to.
When WP# pin is high the Status register is unlocked and can be
written to after a Write Enable instruction, WEL=1.
Status Register is protected and can not be written to again until
the next power-down, power-up cycle.
Status Register is permanently protected and can not be written
to.
Description
(1)
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