S25FL004K Meet Spansion Inc., S25FL004K Datasheet - Page 37

• Manufacturer Part Number: S25FL004K
• Description: 4-mbit / 8-mbit / 16-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

7.13
July 14, 2011 S25FL004K-016K_00_02
Octal Word Read Quad I/O (E3h)
Word Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Word Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a
“Set Burst with Wrap” command prior to E7h. The “Set Burst with Wrap” command can either enable or
disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is enabled, the
data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte page. The output
data starts at the initial address specified in the instruction, once it reaches the ending boundary of the
8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until CS# is
pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section
within a page. See
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are not
required, which further reduces the instruction overhead allowing even faster random access for code
execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word Read
Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in
Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 ¹ 10) on page
nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”).
However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is
raised and then lowered) does not require the E3h instruction code, as shown in
Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) on page
instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is
asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A
“Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal
instructions (see
Figure 7.15 Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10)
CS#
CLK
IO1
IO3
IO0
IO2
Section 7.16, Continuous Read Mode Reset (FFh or FFFFh) on page
Mode 3
Mode 0
Section 7.14, Set Burst with Wrap (77h) on page
D a t a
6
7
A23-16
5
4
S25FL004K / S25FL008K / S25FL016K
0
2
3
0
1
1
4
5
6
7
A15-8
S h e e t
2
2
3
0
1
3
4
6
5
7
A7-0
4
0
2
1
3
5
4
5
7
6
M7-0
6
1
3
0
2
7
Dummy
8
9
5
4
6
7
10
Byte 1
2
3
1
0
39.
11
4
6
7
Byte 2
IO Switches from Input to Output
5
12 13
3
1
2
0
6
7
Byte 3
4
5
14
Figure 7.17, Octal Word
2
0
1
3
38. This reduces the
15
Figure 7.16, Octal
4
6
40).
5
7
3
38. The upper
37