S25FL004K Meet Spansion Inc., S25FL004K Datasheet - Page 29

• Manufacturer Part Number: S25FL004K
• Description: 4-mbit / 8-mbit / 16-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

7.6
July 14, 2011 S25FL004K-016K_00_02
Read Data (03h)
During volatile Status Register write operation (50h combined with 01h), after CS# is driven high, the Status
Register bits will be refreshed to the new values within the time period of t
Electrical Characteristics on page
Refer to
for all status Register bits are 0.
The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the CS# pin low and then shifting the instruction code “03h” followed by a
24-bit address (A23-A0) into the SI pin. The code and address bits are latched on the rising edge of the CLK
pin. After the address is received, the data byte of the addressed memory location will be shifted out on the
SO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream
of data. This means that the entire memory can be accessed with a single instruction as long as the clock
continues. The instruction is completed by driving CS# high.
The Read Data instruction sequence is shown in
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects
on the current cycle. The Read Data instruction allows clock rates from DC to a maximum of f
Electrical Characteristics on page
CLK
CLK
CS#
CS#
SO
SO
SI
SI
= MSB
= MSB
Mode 3
Mode 0
Mode 3
Mode 0
Section 6.1, Status Register on page 16
0
0
1
1
Instruction (01h)
Instruction (03h)
Figure 7.5 Write Status Register Instruction Sequence Diagram
2
2
D a t a
3
3
S25FL004K / S25FL008K / S25FL016K
Figure 7.6 Read Data Instruction Sequence Diagram
4
4
5
High Impedance
5
High Impedance
64). BUSY bit will remain 0 during the Status Register bit refresh period.
64.)
S h e e t
6
6
7
7
7
23 22 21
8
8
6
9
9
Status Register In
for detailed Status Register Bit descriptions. Factory default
Figure
24-Bit Address
5
10
10
4
11 12 13 14 15 16 17
3
7.6. If a Read Data instruction is issued while an
3
28 29 30 31 32
2
2
1
1
0
0
X 14 13 12 11
7
SHSL2
6
33 34 35 36 37 38 39
18 19
5
Data Out 1
(see
4
3
20 21 22 23
Section 8.6, AC
X
2
9
1
R
8
.
0
(See AC
Mode 3
Mode 0
7
Data Out 2
29