S25FL004K Meet Spansion Inc., S25FL004K Datasheet - Page 23

• Manufacturer Part Number: S25FL004K
• Description: 4-mbit / 8-mbit / 16-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

7. Instructions
July 14, 2011 S25FL004K-016K_00_02
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
The instruction set of the S25FL004K, S25FL008K, and S25FL008K consist of thirty five basic instructions
that are fully controlled through the SPI bus (see
with the falling edge of Chip Select (CS#). The first byte of data clocked into the SI input provides the
instruction code. Data on the SI input is sampled on the rising edge of clock with most significant bit (MSB)
first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge CS#. Clock relative timing diagrams for each instruction are included in the figures below.
All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or
Erase must complete on a byte boundary (CS# driven high after a full 8 bits have been clocked) otherwise the
instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while
the memory is being programmed or erased, or when the Status Register is being written, all instructions
except for Read Status Register will be ignored until the program or erase cycle has completed.
SEC
X
X
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TB
X
X
Status Register
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
BP2
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
Table 6.7 S25FL016K Status Register Memory Protection (CMP = 1)
(1)
BP1
0
0
1
1
0
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
D a t a
S25FL004K / S25FL008K / S25FL016K
BP0
X
X
X
0
1
0
1
0
1
1
0
1
0
1
1
0
1
1
0
1
S h e e t
Protected Block(s)
16 thru 31
0 thru 31
0 thru 30
0 thru 29
0 thru 27
0 thru 23
0 thru 15
1 thru 31
2 and 31
4 thru 31
8 thru 31
0 thru 31
0 thru 31
0 thru 31
0 thru 31
0 thru 31
0 thru 31
0 thru 31
0 thru 31
None
Table 7.3
S25FL016K (16 Mbit) Memory Protection
Protected Addresses
000000h – 1FFFFFh
000000h – 1EFFFFh
000000h – 1DFFFFh
000000h – 1BFFFFh
000000h – 0FFFFFh
010000h – 1FFFFFh
020000h – 1FFFFFh
040000h – 1FFFFFh
080000h – 1FFFFFh
100000h – 1FFFFFh
000000h – 1FEFFFh
000000h – 1FDFFFh
000000h – 1FBFFFh
001000h – 1FFFFFh
002000h – 1FFFFFh
004000h – 1FFFFFh
008000h – 1FFFFFh
000000h – 17FFFFh
000000h – 1F7FFFh
to
Table 7.5 on page
None
26). Instructions are initiated
Protected
1,984 kB
1,920 kB
1,792 kB
1,536 kB
1,984 kB
1,920 kB
1,792 kB
1,536 kB
2,044 kB
2,040 kB
2,032 kB
2,016 kB
2,044 kB
2,040 kB
2,032 kB
2,016 kB
Density
1 MB
1 MB
None
All
(2)
Protected Portion
Lower 511/512
Lower 255/256
Lower 127/128
Upper 511/512
Upper 255/256
Upper 127/128
Upper 31/32
Upper 15/16
Lower 31/32
Lower 15/16
Lower 63/64
Upper 63/64
Lower 7/8
Lower 3/4
Lower 1/2
Upper 7/8
Upper 3/4
Upper 1/2
None
All
(2)
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