S25FL004K Meet Spansion Inc., S25FL004K Datasheet - Page 46

• Manufacturer Part Number: S25FL004K
• Description: 4-mbit / 8-mbit / 16-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

7.22
46
Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register
bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruction code
“C7h” or “60h”. The Chip Erase instruction sequence is shown in
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After CS# is driven high, the self-timed Chip Erase instruction will commence
for a time duration of t
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The
BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept
other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the
Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the
Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see
Register Memory Protection (CMP = 0)).
CLK
CS#
SO
SI
CE
.
(See AC Electrical Characteristics on page
Figure 7.25 Chip Erase Instruction Sequence Diagram
Mode 3
Mode 0
S25FL004K / S25FL008K / S25FL016K
0
D a t a
1
Instruction (C7h/60h)
High Impedance
2
S h e e t
3
4
Table
Figure
5
6.2,
64.) While the Chip Erase cycle is in
6
S25FL004K-016K_00_02 July 14, 2011
7.25.
Table
7
6.3, and
Mode 3
Mode 0
Table 6.4
for Status