S25FL004K Meet Spansion Inc., S25FL004K Datasheet - Page 58

• Manufacturer Part Number: S25FL004K
• Description: 4-mbit / 8-mbit / 16-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

7.33
58
Erase Security Registers (44h)
The S25FL004K/S25FL008K/S25FL016K offers three 256-byte Security Registers which can be erased and
programmed individually. These registers may be used by the system manufacturers to store security and
other important information separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction
must be executed before the device will accept the Erase Security Register Instruction (Status Register bit
WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruction code
“44h” followed by a 24-bit address (A23-A0) to erase one of the three security registers.
The Erase Security Register instruction sequence is shown in
after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed.
After CS# is driven high, the self-timed Erase Security Register operation will commence for a time duration
of t
the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY
bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit
in the Status Register is cleared to 0. The Security Register Lock Bits (LB3:1) in the Status Register-2 can be
used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will
be permanently locked, and an Erase Security Register instruction to that register will be ignored (see
Security Register Lock Bits (LB3, LB2, LB1)
SE
(see AC Electrical Characteristics
Security Register #1
Security Register #2
Security Register #3
CLK
CS#
SO
SI
Address
Mode 3
Mode 0
= MSB
Figure 7.37 Erase Security Registers Instruction Sequence
S25FL004K / S25FL008K / S25FL016K
0
1
2
Instruction (44h)
3
on page
A23-16
00h
00h
00h
on page
High Impedance
4
D a t a
5
64). While the Erase Security Register cycle is in progress,
17).
6
S h e e t
7
0 0 0 1 b
0 0 1 0 b
0 0 1 1 b
A15-12
23
8
Figure
22
9
24-bit Address
7.37. The CS# pin must be driven high
S25FL004K-016K_00_02 July 14, 2011
2
29
0 0 0 0 b
0 0 0 0 b
0 0 0 0 b
A11-8
1
30
0
31
Mode 3
Mode 0
Don’t Care
Don’t Care
Don’t Care
A7-0