ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 120

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
UART Interrupt Enable Register
The UARTx_IER register is used to enable and disable the UART interrupts. The
UARTx_IER registers share the same I/O addresses as the UARTx_BRG_H registers. See
Table
Table 56. UART Interrupt Enable Registers(UART0_IER = 00C1h, UART1_IER =
00D1h)
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:5]
4
TCIE
3
MIIE
2
LSIE
1
TIE
0
RIE
56.
Value
000
0
1
0
1
0
1
0
1
0
1
Description
Reserved.
Transmission complete interrupt is disabled.
Transmission complete interrupt is generated when both the
transmit hold register and the transmit shift register are empty.
Modem interrupt on edge detect of status inputs is disabled.
Modem interrupt on edge detect of status inputs is enabled.
Line status interrupt is disabled.
Line status interrupt is enabled for receive data errors:
incorrect parity bit received, framing error, overrun error, or
break detection.
Transmit interrupt is disabled.
Transmit interrupt is enabled. Interrupt is generated when the
transmit FIFO/buffer is empty indicating no more bytes
available for transmission.
Receive interrupt is disabled.
Receive interrupt and receiver time-out interrupt are enabled.
Interrupt is generated if the FIFO/buffer contains data ready to
be read or if the receiver times out.
R
7
0
R
6
0
R
5
0
Universal Asynchronous Receiver/Transmitter
R/W
4
0
R/W
3
0
Product Specification
R/W
2
0
eZ80F92/eZ80F93
R/W
1
0
R/W
0
0
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