ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 243

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

Table 151. External I/O Write Timing (Continued)
PS015313-0508
Wait State Timing for Read Operations
Figure 62
for a Read operation. This WAIT state is generated by setting CS_WAIT to
Chip Select Control Register.
Parameter
T
Note: *At the conclusion of a Write cycle, deassertion of WR always occurs before any change to
ADDR[23:0]
10
DATA[7:0]
INSTRD
(output)
MREQ
ADDR, DATA, CSx, or IORQ.
CSx
X
RD
IN
displays the extension of the memory access signals using a single WAIT state
Abbreviation
Clock Rise to WR Deassertion Delay*
WR Deassertion to ADDR Hold Time
WR Deassertion to DATA Hold Time
WR Deassertion to CSx Hold Time
WR Deassertion to IORQ Hold Time
Figure 62.Wait State Timing for Read Operations
T
CLK
T
WAIT
Product Specification
0.25
0.25
0.25
0.25
Min
Electrical Characteristics
1.6
Delay (ns)
001h
Max
6.5
in the
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