ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 61

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

Table 15. Z80 Bus Mode Write States
PS015313-0508
STATE T1
STATE T2
STATE T3
The Write cycle begins in State T1. The CPU drives the address onto the address bus, the
associated Chip Select signal is asserted.
During State T2, the WR signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU
system clock cycle prior to the end of State T2, additional WAIT states (T
until the WAIT pin is driven High.
During State T3, no bus signals are altered.
Z80
The Z80 bus mode states can be configured for 1 to 15 CPU system clock cycles. In the
figures, each Z80 bus mode state is two CPU system clock cycles in duration.
Figure 10
peripheral during each Z80 bus mode cycle.
System Clock
ADDR[23:0]
®
DATA[7:0]
or IORQ
bus mode Read and Write timing is displayed in
MREQ
WAIT
CSx
WR
RD
on page 55 also display the assertion of 1 wait state (T
Figure 9.Example: Z80 Bus Mode Read Timing
T1
T2
T
CLK
Figure 9
T3
and
Chip Selects and Wait States
Product Specification
WAIT
Figure 10
eZ80F92/eZ80F93
) by the external
WAIT
) are asserted
Figure 9
on page 55.
and
54