ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 138

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
SPI Signals
The four basic SPI signals are:
1. MISO (Master In, Slave Out)
2. MOSI (Master Out, Slave In)
3. SCK (SPI Serial Clock)
4. SS (Slave Select)
These SPI signals are discussed in the following paragraphs. Each signal is described in
both MASTER and SLAVE modes.
Master In, Slave Out
The Master In, Slave Out (MISO) pin is configured as an input in a master device and as
an output in a slave device. It is one of the two lines that transfer serial data, with the msb
sent first. The MISO pin of a slave device is placed in a high-impedance state if the slave
is not selected. When the SPI is not enabled, this signal is in a high-impedance state.
Master Out, Slave In
The Master Out, Slave In (MOSI) pin is configured as an output in a master device and as
an input in a slave device. It is one of the two lines that transfer serial data, with the msb
sent first. When the SPI is not enabled, this signal is in a high-impedance state.
Slave Select
The active Low Slave Select (SS) input signal is used to select the SPI as a slave device. It
must be Low prior to all data communication and must stay Low for the duration of the
data transfer.
The SS input signal must be High for the SPI to operate as a master device. If the SS signal
goes Low, a Mode Fault error flag (MODF) is set in the SPI_SR register. See SPI Status
Register (SPI_SR) on page 137 for more information.
ENABLE
DATAIN
CLKIN
SS
MOSI
SCK
Bit 0
8-Bit Shift Register
Figure 30.SPI Slave Device
SLAVE
Bit 7
MISO
DATAOUT
Product Specification
Serial Peripheral Interface
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