ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 73
ez80f92
Manufacturer Part Number
ez80f92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F92.pdf
(261 pages)
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PS015313-0508
System Clock
ADDR[23:0]
DATA[7:0]
or IORQ
DTACK
MREQ
CSx
R/W
DS
AS
Switching Between Bus Modes
Each time the bus mode controller must switch from one bus mode to another, there is a
one-cycle CPU system clock delay. An extra clock cycle is not required for repeated
access in any of the bus modes; nor is it required when the eZ80F92 device switches to
eZ80
asynchronous nature of these bus protocols, the extra delay does not impact peripheral
communication.
®
bus mode. The extra clock cycles are not shown in the timing examples. Due to the
Figure 18. Example: Motorola Bus Mode Write Timing
S0
S1
S2
S3
S4
S5
Chip Selects and Wait States
Product Specification
S6
eZ80F92/eZ80F93
S7
66
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