ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 52

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

Interrupt Controller
PS015313-0508
Maskable Interrupts
The interrupt controller on the eZ80F92 device routes the interrupt request signals from
the internal peripherals and external devices (via the GPIO pins) to the CPU.
On the eZ80F92 device, all maskable interrupts use the CPU’s vectored interrupt function.
Table 11
maskable interrupt sources are listed in order of priority, with vector
est-priority interrupt. The full 16-bit interrupt vector is located at starting address {I[7:0],
IVECT[7:0]} where I[7:0] is the CPU’s Interrupt Page Address Register.
Table 11. Interrupt Vector Sources by Priority
Your program must store the starting address of the interrupt service routine (ISR) in the
two-byte interrupt vector locations. For example, for ADL mode the two-byte address for
the SPI interrupt service routine would be stored at {
1Fh
Note: Absolute locations 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h, and 66h are reserved for hardware
Vector
0Ah
0Ch
0Eh
00h
02h
04h
06h
08h
10h
12h
14h
16h
18h
}. In Z80
reset, NMI, and the RST instruction.
lists the low-byte vector for each of the maskable interrupt sources. The
UART 0
Source
Unused
Unused
Unused
Unused
PRT 0
PRT 1
PRT 2
PRT 3
PRT 4
PRT 5
®
Flash
RTC
mode, the two-byte address for the SPI interrupt service routine would be
Vector
1Ah
1Ch
1Eh
2Ah
2Ch
2Eh
20h
22h
24h
26h
28h
30h
32h
UART 1
Port B 0
Port B 1
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Source
SPI
I
2
C
Vector
3Ah
3Ch
3Eh
4Ah
4Ch
34h
36h
38h
40h
42h
44h
46h
48h
00h
, I[7:0], 1Eh} and {
Port B 7
Port C 0
Port C 1
Port C 2
Port C 3
Port C 4
Port C 5
Port C 6
Port B 2
Port B 3
Port B 4
Port B 5
Port B 6
Source
Product Specification
00h
Vector
eZ80F92/eZ80F93
5Ch
4Eh
5Ah
5Eh
50h
52h
54h
56h
58h
60h
62h
64h
66h
Interrupt Controller
being the high-
00h
Port C 7
Port D 0
Port D 1
Port D 2
Port D 3
Port D 4
Port D 5
Port D 6
Port D 7
Source
Unused
Unused
Unused
Unused
, I[7:0],
45