at42qt1481 ATMEL Corporation, at42qt1481 Datasheet - Page 14

• Manufacturer Part Number: at42qt1481
• Description: 48-key Qmatrix Ic
• Manufacturer: ATMEL Corporation

2.12
2.13
14
Power Supply Considerations
Startup/Calibration Times
AT42QT1481
For Vdd information see
As the QT1481 uses the power supply as an analog reference, the power should be very clean
and come from a separate regulator. A standard inexpensive Low Dropout (LDO) type regulator
should be used; it should not also be used to power other loads such as relays or other high
current devices. Load shifts on the output of the LDO can cause Vdd to fluctuate enough to
cause false detection or sensitivity shifts.
Ceramic 0.1 µF bypass capacitors should be placed very close and routed with short traces to all
power pins of the IC. There should be at least three such capacitors around the part.
The QT1481 employs a rigorous initialization and self-check sequence for EN60730 compliance.
If the self-tests are passed, the last step in this sequence enables the serial communication
interfaces. The communication interfaces are not enabled if a safety critical fault is detected
during the startup sequence. The QT1481 requires initialization times as follows:
The QT1481 determines a reference level for each key by calibrating all the keys immediately
after initialization. Each key is calibrated independently and in parallel with all other enabled
keys. Calibration takes between 11 and 62 keyscan cycles; each cycle being made up of one
sample from each enabled key. The QT1481 ends calibration for a key if its reference has
converged with the signal DC level. The calibration time is shortest when the keys signals are
stable, typically increasing with increasing noise levels to the maximum of 62 keyscan cycles.
An error is reported for each key where calibration continues for the maximum number of
keyscan cycles and the key's reference does not appear to have converged with the signals DC
level. Noise levels can vary from key to key such that some keys may take longer to calibrate
than others. However, the QT1481 can report during this interval that the key(s) affected are still
in calibration via the QT1481 status bits.
times per key versus dwell time and burst length for all 48 keys enabled. The values given
assume that MSYNC = off, SDC = 0 and STS_DEBUG = 0.
Table 2-2.
Setups
BL = 0 (16 pulses)
DWELL = 0 (125 ns)
FREQ0 = 0
Signal level = 200 counts
BL = 3 (64 pulses)
DWELL = 15 (9.9 µs)
Signal level = 400 counts
1. Normal reset to ability to communicate: 110 ms.
2. From very first power-up to ability to communicate:
3. From power-up to ability to communicate:
2,200 ms (one time event to initialize all of EEPROM, or to recover EEPROM copy from
Flash in the event of EEPROM corruption).
140 ms in the event the setups have been changed and the part needs to back up the
EEPROM to Flash.
Keyscan Cycle and Calibration Times
Section 6.1
Keyscan Cycle Time
17 ms
6 ms
and
Section 6.2 on page
Table 2-2
Calibration Time (min) Calibration Time (max)
shows keyscan cycle times and calibration
187 ms (11 x 17)
66 ms (11 x 6)
59.
1054 ms (62 x 17)
372 ms (62 x 6)
9621B–AT42–06/11