at42qt1481 ATMEL Corporation, at42qt1481 Datasheet - Page 24

• Manufacturer Part Number: at42qt1481
• Description: 48-key Qmatrix Ic
• Manufacturer: ATMEL Corporation

24
AT42QT1481
Wake operation: The QT1481 can be configured to automatically sleep. The host must awaken
the QT1481, when required, with a 8.5 µs (minimum) low level on the WS pin. With the Rx line
tied to WS the QT1481 can be awaked with a dummy byte from the host. The first received
UART byte from the host after a wake should be a 0xFF; any other byte value could create a
framing error. The start bit of the 0xFF forms a convenient narrow wake pulse without being
long enough to be interpreted as a byte during the wake operation.
There is an interval of approximately 1.5 ms from the pulse on WS before the QT1481 is able to
resume processing. Transmissions to the QT1481 within this interval are discarded.
The recommended method to re-establish communications after Wake from Sleep is to send a
0x0F (“Get Last Command” command) repeatedly until the correct response comes back (the
command's ow n complement, that is, 0xF0).
Rx – Receive async data. This pin is an input only.
Tx – Transmit async data. Drives out when transmitting but floats within 10 µs of the end of the
stop bit, to allow bussing with several similar devices. Tx should idle high, and it includes an
internal 20 k – 50 k resistor to Vdd. Tx is push-pull when transmitting data for good drive
characteristics.
Figure 3-3.
UART transmission parameters are:
Baud rate:
Start bits:
Data bits:
Parity:
Stop bits:
DRDY in UART mode:
DRDY is bidirectional in UART mode and can be pulled down by either the QT1481 or the host
(wire-AND), so that either device can be inhibited from sending data until the other is ready. The
host should obey this control line or transmission errors can occur. The host should grant a
10 µs grace period after clamping DRDY low in which it can still accept the start bit of a
transmission from the QT1481.
As explained in
receives a byte; there can be up to a 100 µs delay from the end of the stop bit before DRDY goes
low. Sampling of DRDY by the host should occur 100 µs after the byte has been fully sent. If
DRDY is already high at this point, or becomes high, then it is clear to send.
Host MCU
P_IN
Rx
Tx
Communications Signals – UART
Section 3.2 on page
9600 – 115,200
1
8
None
1
Section 3.2 on page 20
20, DRDY is not clamped low immediately after the QT1481
QT1481
Tx
Rx
DRDY
applies.
9621B–AT42–06/11