at42qt1481 ATMEL Corporation, at42qt1481 Datasheet - Page 22

• Manufacturer Part Number: at42qt1481
• Description: 48-key Qmatrix Ic
• Manufacturer: ATMEL Corporation

SCK – SPI clock; input only clock from host. The host must shift out data on the falling SCK
edge, the QT1481 clocks data in on the rising edge. The QT1481 likewise shifts data out on the
falling edge of SCK back to the host so that the host can shift the data in on the rising edge.
Note:
Important: SCK must idle high; it should never float.
SS – Slave select; input only; acts as a framing signal to the sensor from the host. SS must be
low before and during reception of data from the host. It must not go high again until the SCK
line has returned high; SS must idle high. This pin includes an internal pull-up resistor of 20 k –
50 k. When SS is high, MISO floats.
DRDY – Data Ready; when high – indicates to the host that the QT1481 is ready to send or
receive data. This pin idles high. This pin includes an internal pull-up resistor of 20 k – 50 k.
In SPI mode this pin is an output only (that is, open drain with internal pull-up resistor).
The MISO pin on the QT1481 floats in three-state mode between bytes when SS is high. This
facilitates multiple devices on one SPI bus.
Null Bytes: When the QT1481 responds to a command with one or more response bytes, the
host should issue a null command (0x00) to get the response bytes back. The host should not
send new commands until all the responses are accepted back from the QT1481 from the prior
command via nulls.
New commands attempted during intermediate byte transfers are ignored.
Wake operation: The QT1481 can be configured to automatically sleep. The host must awaken
the QT1481, when required, with a 8.5 µs minimum low level on the WS pin. With the SS line
tied to WS, the host can simply toggle SS low for 8.5 µs minimum to wake the QT1481. The host
should not send an actual SPI byte to prevent the QT1481 from seeing a byte it cannot properly
interpret due to timing errors during wake-up. Alternatively, SS can be driven low 8.5 µs before
the first SCK of each transfer.
There is an interval of approximately 1.5 ms from the pulse on WS before the QT1481 is able to
resume processing. Transmissions to the QT1481 within this interval are discarded.
The recommended method to re-establish communications after Wake from Sleep is to send the
QT1481 a 0x0F (“Get Last Command” command) repeatedly until the correct response comes
back (the command's own complement, that is, 0xF0).
SPI Line Noise: In some designs it is necessary to run SPI lines over ribbon cable across a
lengthy distance on a PCB. This can introduce ringing, ground bounce, and other noise
problems which can introduce false SPI clocking or false data. Simple RC networks and slower
data rates are helpful to resolve these issues.
A CRC is appended to responses in order to detect transmission errors to a high level of
certainty.
AT42QT1481
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9621B–AT42–06/11