at42qt1481 ATMEL Corporation, at42qt1481 Datasheet - Page 65

• Manufacturer Part Number: at42qt1481
• Description: 48-key Qmatrix Ic
• Manufacturer: ATMEL Corporation

Appendix B.
9621B–AT42–06/11
DEBUG Output
The QT1481 includes a debug interface which may be used for observing many internal
operating variables, in real time, even while the part is actively communicating with a host over
either the SPI or UART serial interfaces. The Debug interface provides a useful aid during
product development and uses two pins, one for clock and one for data, to stream data out of the
part.
If STS_DEBUG is enabled in the STS Setups byte the QT1481 streams a 465-byte frame of
data out of the two debug pins after most keyscan cycles. A debug frame is not transmitted at
the end of each keyscan cycle if the interval required for each keyscan cycle is short enough that
the debug receiver might be overwhelmed by the debug data rate. The transmission format is
compatible with Atmel's Plug-in USB card (Part Number 9206) and the data can be viewed using
Atmel's Hawkeye PC software (contact Atmel for information).
interface details.
Table B-1.
The meaning of each byte in the 465-byte frame is described in
Table B-2.
Debug Clock output
Debug Data output
Data valid
Data changing
Clock frequency
Blank time between byte transmissions
Frame transmission time
Byte transmission order
Frame Byte #
10
11
0
1
2
3
4
5
6
7
8
9
Debug Output Data Frame
Debug Interface
Description
Detect status for keys 0 (bit0) to 7 (bit7), one bit per key
Detect status for keys 8 (bit0) to 15 (bit7), one bit per key
Detect status for keys 16 (bit0) to 23 (bit7), one bit per key
Detect status for keys 24 (bit0) to 31 (bit7), one bit per key
Detect status for keys 32 (bit0) to 39 (bit7), one bit per key
Detect status for keys 40 (bit0) to 47 (bit7), one bit per key
Device status (identical to first byte returned from command 0x06)
Count of keys declaring detect
A 6-bit unsigned value encoding the first or only key to be touched, in the range 0 – 47
Time remaining before host reset pulse is issued at STATUS pin. Each count is 10 ms
Time remaining until normal drift compensation is resumed. Each count is 100 ms
Time remaining before QT1481 tries to sleep (if enabled). Each count is 100 ms
Pin 43 (Dbg_Clk)
Pin 40 (Dbg_Data)
Clock high
Clock low
Approximately 500 kHz
5.5 µs
8.8 ms
Most significant bit (MSB) first
Table
Table B-1
B-2.
AT42QT1481
shows the Debug
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