at42qt1481 ATMEL Corporation, at42qt1481 Datasheet - Page 15

• Manufacturer Part Number: at42qt1481
• Description: 48-key Qmatrix Ic
• Manufacturer: ATMEL Corporation

2.14
2.15
9621B–AT42–06/11
Reset Input
Detection Integrators
Should communications with the QT1481 be lost the RST pin can be used to reset the QT1481
to simulate a power-down cycle, in order to then bring the QT1481 up into a known state. The
pin is active low, and a low pulse lasting at least 10 µs must be applied to this pin to cause a
reset.
To provide for proper operation during power transitions the QT1481 has an internal brownout
detector set to 4V.
The reset pin has an internal 30 k – 60 k resistor. A 2.2 µF capacitor plus a diode to Vdd can
be connected to this pin as a traditional reset circuit, but this is not necessary.
A Force Reset command, 0x04, also generates an equivalent hardware reset where the device
is still in communication with the host. Where the QT1481has detected a failure of one of the
internal EN60730 checks and has subsequently locked up in an infinite loop, only a power cycle
or an external hardware reset can restore normal operation. It is strongly recommended that the
host has control over the RST pin.
If an external hardware reset is not used, this pin may be connected to Vdd or left floating.
See also
The QT1481 features a detection integration mechanism, which acts to confirm a detection in a
robust fashion. A per-key counter is incremented each time the key has exceeded its threshold
and stayed there for a number of acquisitions. When this counter reaches a preset limit the key
is finally declared to be touched.
For example, if the limit value is 10, then the QT1481 has to exceed its threshold and stay there
for 10 acquisitions in succession without going below the threshold level, before the key is
declared to be touched. If, on any acquisition, the signal is not seen to exceed the threshold
level, the counter is cleared and the process starts from the beginning.
The QT1481 uses a two-tier confirmation mechanism having two such counters for each key.
These can be thought of as inner loop and outer loop confirmation counters.
The inner counter is referred to as the fast-DI; this acts to attempt to confirm a detection via rapid
successive acquisition bursts, at the expense of delaying the sampling of the next key. Each key
has its own fast-DI counter and limit value; these limits can be changed via the Setups block on
a per-key basis.
The outer counter is referred to as the normal-DI; this DI counter increments whenever the
fast-DI counter has reached its limit value. If a fast-DI counter failed to reach its terminal count,
the corresponding normal-DI counter is also reset. The normal-DI counter also has a limit value
which is settable on a per-key basis.
If a normal-DI counter reaches its terminal count, the corresponding key is declared to be
touched and becomes active. Note that the normal-DI can only be incremented once per
complete keyscan cycle, i.e. more slowly, whereas the fast-DI is incremented ‘on the spot’
without interruption (at the same burst spacing timing).
The net effect of this mechanism is a multiplication of the inner and outer counters and hence a
highly noise-resistant sensing method. If the inner limit is set to 5, and the outer to 3, the net
effect is 5 x 3 = 15 successive threshold crossings to declare a key as active.
Section 5.5 on page
42.
AT42QT1481
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