at42qt1481 ATMEL Corporation, at42qt1481 Datasheet - Page 47

• Manufacturer Part Number: at42qt1481
• Description: 48-key Qmatrix Ic
• Manufacturer: ATMEL Corporation

5.15
5.16
9621B–AT42–06/11
Restart Interrupted Burst – RIB
Sleep Drift Compensation – SDC
The sync occurs only at the burst for the lowest numbered enabled key in the matrix. If it does
not sleep at the end of the matrix scan, the QT1481 waits for the sync signal for up to 100 ms
after the end of a preceding full matrix scan, then the matrix is scanned in its entirety again. If the
QT1481 sleeps, it waits indefinitely for the mains sync.
The sync signal drive should be a buffered logic signal, or perhaps a diode-clamped signal, but
never a raw AC signal from the mains. If mains sync is enabled and sleep is disabled, the
QT1481 synchronizes to the falling sync edge. However, if both mains sync and sleep are
enabled, the QT1481 is sensitive to a low level on WS. A first matrix scan occurs when the low
level is first detected, and further matrix scans occur for as long as WS is held low. It is therefore
recommended that WS is driven low for less than a single matrix scan time.
Since Noise sync is highly effective and inexpensive to implement, it is strongly advised to take
advantage of it anywhere there is a possibility of encountering low frequency (50/60 Hz) electric
fields. Atmel’s QmBtn software can show such noise effects on signals, and therefore assist in
determining the need to make use of this feature.
If the sync feature is enabled but no sync signal exists, the sensor continues to operate but with
a delay of 100 ms from the end of one scan to the start of the next, and hence has a slow
response time. A failed Sync signal (one exceeding a 100 ms period) causes an error flag (see
command 0x06). From reset, the QT1481 first reports a mains sync error after initialisation
followed by a delay of 100 ms waiting for the sync signal. This time interval may be determined
by adding 100 ms to the initialisation times stated in
MSYNC Default value:
MSYNC Possible range:
The RIB parameter in Setups allows a burst to be interrupted, and restarted, by host
communications over the serial bus. The QT1481 has limited processing resources available
such that a burst and host communication cannot both be serviced simultaneously. One must
give way to the other. This setup lets the designer prioritize one over the other.
If RIB is configured on, a burst can be interrupted by a host communication, and is automatically
restarted.
If RIB is configured off, bursts cannot be interrupted but, rather, the host communication is
delayed until the burst has completed. The DRDY low period is stretched by the QT1481 during
the burst.
This function is programmed on a global basis. See
RIB Default value: 0 (Off)
RIB Possible range: 0, 1 (off, On)
See also
SDC allows the QT1481 to be configured for automatic sleep, and for modified drift
compensation when sleep is enabled. Whenever the QT1481 goes to sleep, the whole device is
shutdown, including the clock generator. All operations are stopped including matrix scanning
and timers, which results in the internal time keeping running very slow and, in particular, drift
compensation runs at a rate much slower than configured by NDRIFT and PDRIFT.
Section 5.4 on page 40
0 (Off)
0, 1 (Off, On)
Sleep, NDRIFT and PDRIFT.
Table 5-8 on page
Section 2.13 on page
58.
AT42QT1481
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