at42qt1481 ATMEL Corporation, at42qt1481 Datasheet - Page 26

• Manufacturer Part Number: at42qt1481
• Description: 48-key Qmatrix Ic
• Manufacturer: ATMEL Corporation

4. Control Commands
4.1
4.2
26
Introduction
Null Command – 0x00
AT42QT1481
Refer to
Suggested command sequencing: See
The QT1481 features a set of commands which are used for control and status reporting. The
host device has to send the command to the QT1481 and await a response.
SPI mode: While waiting the host should delay for 100 µs from the end of the command, then
start to check if DRDY is, or goes, high. If it is high, then the host master can clock out the
resulting byte(s).
Command timeouts in SPI mode: Where a command involves multiple byte transfers to the
QT1481, each byte must be transmitted within 110 ms ±5 ms of the prior byte or the command
times out. Where a command involves a multiple byte response from the QT1481, the entire
command must be completed within 110 ms ±5 ms or the command times out. No error is
reported for this condition. The command simply ceases.
UART mode: After the command is sent, the QT1481 sends back the response, usually starting
within 1 ms. The host can clamp DRDY low (wire-AND logic) to inhibit a response (for up to
110 ms) if the host is not able to receive the transmission for a while.
Command timeouts in UART mode: Where a command involves multibyte transfers in either
direction, each byte must be transmitted within 110 ms ±5 ms of the prior byte or the command
times out. No error is reported for this condition. The command simply ceases.
Word return byte order: Where a word or long word is returned (16 or 24 bit number or bit
pattern) the low order byte is sent or received first.
Response delays: The QT1481 requires processing time to complete command requests and
respond with an answer to the host. These timings are the same for SPI and UART modes. Most
commands respond with data in 1 ms maximum; timing parameters U2 and U3 in
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Add 15 ms to all stated response times if the STS_DEBUG Setup is enabled.
This command is used to shift back data from the QT1481 in SPI mode. Since the host device is
always the master in SPI mode, and data is clocked in both directions, the Null command is
required frequently to act as a placeholder where the desire is to only get data back from the
QT1481, not to send a command.
In SPI communications, when the QT1481 responds to a command with one or more response
bytes, the host can issue a new command instead of a null on the last byte shift operation.
New commands during intermediate byte shift-out operations are ignored, and null bytes should
always be used.
0x01 (Setups upload):
0x02 (Low Level Cal and Offset):
Table 4-5 on page 36
are therefore 1 ms maximum for these commands. The exceptions are:
for further details.
Section 4.19 on page
<20 ms
<20 ms
33.
9621B–AT42–06/11
Figure 3-4 on