at42qt1481 ATMEL Corporation, at42qt1481 Datasheet - Page 21

• Manufacturer Part Number: at42qt1481
• Description: 48-key Qmatrix Ic
• Manufacturer: ATMEL Corporation

3.3
9621B–AT42–06/11
SPI Communications
Serial communications pacing is controlled by this pin. Use of DRDY is critical to successful
communications with the QT1481. In either UART or SPI mode, the host is permitted to perform
a data transfer only when DRDY has returned high. Additionally, in UART mode, the QT1481
delays responses to the host if DRDY is being held low by the host.
After each byte transfer DRDY goes low after a short delay and remains low until the QT1481 is
ready for another transfer. A short delay occurs before DRDY is driven low because the QT1481
may otherwise be busy and requires a finite time to respond.
DRDY may go low for a few microseconds only. During the period from the end of one transfer
until DRDY goes low and back high again, the host should not perform another transfer.
Therefore, before each byte transmission the host should first check that DRDY is high again.
If the host wants to perform a byte transfer with the QT1481 it should behave as follows:
In most cases it takes up to 3 ms for DRDY to return high again. However, this time is longer with
some commands or if the STS_DEBUG setup is enabled, as follows:
Other DRDY specifications:
No special configuration is required to make the QT1481 operate in SPI mode. The QT1481
responds on the interface which is used to command it. SPI and UART interfaces cannot be
used simultaneously.
SPI communications operate in slave mode only, and obey DRDY control signaling. The
clocking is as follows:
SPI mode requires five signals to operate (see
MOSI – Master out / Slave in data pin; used as an input for data from the host (master). This pin
should be connected to the MOSI (DO) pin of the host device.
MISO – Master in / Slave out data pin; used as an output for data to the host. This pin should be
connected to the MISO (DI) pin of the host. MISO floats in three-state mode between bytes
when SS is high to facilitate multiple devices on one SPI bus.
1. Wait at least 100 µs after the previous transfer (time S5 in
2. Wait until DRDY is high (it may already be high).
3. Perform the next transfer with the QT1481.
DRDY is guaranteed to go low before this 100 µs expires).
0x01 (Setups load):
0x02 (Low Level Cal and Offset):
Add 15 ms to the above times if the STS_DEBUG setup is enabled.
Min time DRDY is low:
Max time DRDY is low after reset:
Clock idle:
Clock shift out edge:
Clock data in edge:
Max clock rate:
High
Falling
Rising
4 MHz
<20 ms
<20 ms
1 µs
100 ms
Figure 3-1 on page
Figure 3-2 on page
23):
AT42QT1481
23:
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